Xilinx Virtex-6 FPGA User Manual

278 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 5: Board Design Guidelines
Partially Unused Quad Column
If only a portion of the Quads is used, there are two possible scenarios that affect how the
Quad pins can be connected.
For the first scenario, if the Virtex-6 FPGA is one of the devices with a north bank and a
south bank of Quads and none of the devices in the south bank are used in the application,
the unused Quad pins should be connected as shown in Table 5-4. The analog power
supply pins for the south bank are connected to ground. In this scenario, grounding the
analog power supply pins applies only to the south bank of Quads because none of the
Quads in the south group are used.
For the second scenario, Table 5-5 shows the connections to the unused Quads when no
Quad bank is completely unused.
Note:
The analog power supplies must be connected.
MGTRREF
(1)
GND
Notes:
1. This is the only scenario when the RCAL pins can be connected to ground. In all other scenarios, these
pins must be connected for normal operation.
2. The GTX banks can only be left unpowered if the transceivers in the bank will never be used, or if the
transceivers in the bank will never bypass the TX or RX buffers. Refer to TX Buffer Bypass, page 155
and RX Buffer Bypass, page 231 for more information.
Table 5-3: Unused Quad Column Connections (Cont’d)
Quad Pin or Pin Pair of the Unused Column Connection
Table 5-4: Unused Quad Pin Connections for a Partially Unused Column
Pin or Pin Pair of the Unused Quads Bank Connection
MGTAVCC North MGTAVCC
MGTAVTT North MGTAVTT
MGTREFCLKP/MGTREFCLKN North FLOAT
MGTRXP/MGTRXN North GND
MGTTXP/MGTTXN North FLOAT
MGTAVTTRCAL North AVTT and RCAL precision resistor
MGTRREF North RCAL precision resistor
MGTAVCC
(1)
South GND
MGTAVTT
(1)
South GND
MGTREFCLKP/MGTREFCLKN South FLOAT
MGTRXP/MGTRXN South GND
MGTTXP/MGTTXN South FLOAT
Notes:
1. Connection if all Quads in the south bank are not used.
2. The south bank can only be left unpowered if the transceivers in the south bank will never be used, or
if the transceivers in the south bank will never bypass the TX or RX buffers. Refer to TX Buffer Bypass,
page 155 and RX Buffer Bypass, page 231 for more information.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English