Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 291
UG366 (v2.5) January 17, 2011
Hot Swapping Devices
Crosstalk
Crosstalk is a major contributor to degradation in the performance of a GTX transceiver.
The mechanisms for crosstalk are aggressor signals coupling into signal traces and/or
coupling into the GTX power supplies. The latter is the most common mechanism and
often the most damaging. Noise coupled into the power supply can corrupt the entire
transceiver circuit rather than just a single lane, as in the case of coupling into signal traces.
Also, the effect of noise coupled into the power supply is that the symptoms are often more
difficult to interpret because the noise is integrated with the normal signals in the
transceiver. The result is degradation in the performance of the transceiver that reveals
itself as noise in the transmitter output and reduced jitter tolerance in the receiver.
To avoid performance degradation from crosstalk:
• Monitor the exposure of power planes to other circuits on the board, such as data lines
for memory interfaces and processor buses.
• Provide adequate filtering to the GTX power supplies near the point of the load. The
amount of filtering should be determined by the magnitude and frequency of the
signal from potential noise sources. Noise on the GTX power supplies should be kept
below 10 mV
PP
from 10 kHz to 80 MHz.
• Be aware of the return current paths of signal traces in the vicinity of the GTX power
distribution network. Besides broadband and edge coupling of traces on the same or
adjacent layers, coupling from aggressor traces can occur if the aggressor signal is
propagating from one layer to another, where each layer has a different reference
plane. As the signal propagates through the portion of the via that does not have a
return current path, it generates return currents in the next lowest impedance
structure on the board. That victim can be a signal or power via for the GTX
transceivers.
Hot Swapping Devices
In many applications, the device connected to the transceiver data pins is pluggable, and
the device must often be installed while the FPGA is already powered and configured, i.e.,
hot-swappable or hot-pluggable. The Virtex-6 FPGA GTX transceivers support hot
swapping. The Virtex-6 FPGA transceivers continue to function if the far-end receiver or
transmitter is removed or installed. A recommended practice for hot-pluggable devices is
to use a connector with staged pins so that the ground pins make contact prior to the other
connector pins. This ensures that a reliable path to ground is present when the other device
pins make contact.
SelectIO Usage Guidelines
Because a GTX transceiver’s performance can degrade in an environment flooded with
SelectIO™ interface activity, it is important to have guidelines for SelectIO interface usage
that minimize the impact on GTX transceiver performance.
The pinout for the Virtex-6 FPGA package maintains a physical separation between the
GTX transceiver pins and the SelectIO interface pins. Because of this separation in the
package pinout, no SelectIO interface pins must be excluded when using the GTX
transceivers.
Even though the Virtex-6 FPGA package pinout eliminates the crosstalk between SelectIO
interface and the GTX transceiver pins due to pin adjacency, it is still possible to induce
crosstalk on the PCB. Therefore, when routing signals on the PCB:
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English