Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 257
UG366 (v2.5) January 17, 2011
RX Gearbox
Enabling the RX Gearbox
To enable the RX gearbox for the GTX transceiver, the RXGEARBOX_USE attribute is set to
TRUE. Bit 2 of the GEARBOX_ENDEC attribute must be set to 0 to enable the gearbox
decoder. The decoder controls the GTX transceiver's TX gearbox and RX gearbox. The TX
gearbox and RX gearbox use the same mode.
RX Gearbox Operating Modes
The RX gearbox operates the same in either external sequence counter mode or internal
sequence counter mode. The RX gearbox only supports 2-byte and 4-byte logic interfaces
to the FPGA logic. A 1-byte logic interface is not supported.
As shown in Figure 4-45, either mode uses the RXDATA, RXHEADER,
RXDATAOUTVALID, and RXHEADEROUTVALID outputs in addition to the
RXGEARBOXSLIP input.
The RX gearbox internally manages all sequencing, which differs from the TX gearbox
option of either internal or external sequencing. Depending on whether a 2-byte or a 4-byte
interface is used, RXDATAOUTVALID and RXHEADEROUTVALID assert and deassert
for different periods of length. The RX gearbox encounters similar data and header pauses
found in the TX gearbox. Figure 4-46 shows such a pause in addition to
RXHEADERVALID asserting every other cycle and RXDATAVALID being deasserted for
one cycle.
X-Ref Target - Figure 4-45
Figure 4-45: RX Gearbox in Either Internal or External Sequence Mode
RXGEARBOXSLIP
RXHEADER[2:0]
RXDATA[15:0] or RXDATA[31:0]
RX Gearbox
(in GTX Transceiver)
Design in FPGA
Logic
UG366_c4_42_051509
RXDATAOUTVALID
RXHEADEROUTVALID
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English