Xilinx Virtex-6 FPGA User Manual

218 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
The GTX transceiver includes an alignment block that can be programmed to align specific
commas to various byte boundaries, or to manually align data using attribute settings (see
Figure 4-22) SONET A1/A2 alignment is possible using comma double mode. The block
can be bypassed to reduce latency if it is not needed.
Enabling Comma Alignment
To enable the comma alignment block, the RXCOMMADETUSE port is driven High.
RXCOMMADETUSE is driven Low to bypass the block completely for minimum latency.
Configuring Comma Patterns
To set the comma pattern that the block searches for in the incoming data stream, the
MCOMMA_10B_VALUE, PCOMMA_10B_VALUE, and COMMA_10B_ENABLE
attributes are used. The comma lengths depend on RX_DATA_WIDTH (see Table 4-56,
page 269). Figure 4-23 shows how the COMMA_10B_ENABLE masks each of the comma
values to allow partial pattern matching. Figure 4-23 shows how a COMMA is combined
with COMMA_ENABLE to make a wildcarded comma for a 20-bit internal comma.
If COMMA_DOUBLE is TRUE, the MCOMMA and PCOMMA patterns are combined so
that the block searches for two commas in a row. The number of bits in the comma depends
X-Ref Target - Figure 4-22
Figure 4-22: Parallel Data View of Comma Alignment
TX Parallel Data RX Parallel Data
Data0
Comma
Data1
Data2
Non-aligned
Data
Comma
Data1
Data2
Time
UG366_c4_20_051509
X-Ref Target - Figure 4-23
Figure 4-23: Comma Pattern Masking
0101111100
xxx1111100
0001111111
MCOMMA_10B_VALUE
or
PCOMMA_10B_VALUE
Pattern required
for comma detection
(x = don’t care)
COMMA_10B_ENABLE
UG366_c4_21_051509
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English