Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 37
UG366 (v2.5) January 17, 2011
Simulation
/FPGA Features & Design/IO Interfaces
See Figure 1-4.
3. Double-click V6 GTX Wizard to launch the Wizard.
Simulation
Functional Description
Simulations using GTX transceivers have specific prerequisites that the simulation
environment and the test bench must fulfill.
The Synthesis and Simulation Design Guide explains how to set up the simulation
environment for supported simulators depending on the used Hardware Description
Language (HDL). This design guide can be downloaded from the Xilinx website.
The prerequisites for simulating a design with GTX transceivers are:
• Simulator with support for SecureIP models, which are encrypted versions of the
Verilog HDL used for implementation of the modeled block.
SecureIP is a new IP encryption methodology. To support SecureIP models, a Verilog
LRM - IEEE Std 1364-2005 encryption compliant simulator is required.
• Mixed-language simulator for VHDL simulation.
X-Ref Target - Figure 1-4
Figure 1-4: Virtex-6 FPGA GTX Transceiver Wizard
UG366_c1_04_010710
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English