Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 143
UG366 (v2.5) January 17, 2011
TX 8B/10B Encoder
TX 8B/10B Encoder
Functional Description
Many protocols use 8B/10B encoding on outgoing data. 8B/10B is an industry-standard
encoding scheme that trades two bits of overhead per byte for improved performance. The
GTX transceiver includes an 8B/10B encoder to encode TX data without consuming FPGA
resources. If encoding is not needed, the block can be disabled to minimize latency.
8B/10B Bit and Byte Ordering
8B/10B encoding requires bit a0 to be transmitted first, and the GTX transceiver always
transmits the right-most bit first. To match with 8B/10B, the 8B/10B encoder in the GTX
transceiver automatically reverses the bit order (Figure 3-12).
For the same reason, when a 2-byte interface is used, the first byte to be transmitted (byte 0)
must be placed on TXDATA[7:0], and the second placed on TXDATA[15:8]. When a 4-byte
interface is used, byte 0 must be placed on TXDATA[7:0], byte 1 must be placed on
TXDATA[15:8], byte 2 must be placed on TXDATA[23:16], and byte 3 must be placed on
TXDATA[31:24]. This placement ensures that the byte 0 bits are all sent before the byte 1
bits, as required by 8B/10B encoding.
X-Ref Target - Figure 3-12
Figure 3-12: 8B/10B Encoding
Transmitted
Last
a
0
b
0
c
0
d
0
e
0
i
0
f
0
g
0
h
0
j
0
a
0
b
0
c
0
d
0
e
0
i
0
f
0
g
0
h
0
j
0
a
1
b
1
c
1
d
1
e
1
i
1
f
1
g
1
h
1
j
1
a
2
b
2
c
2
d
2
e
2
i
2
f
2
g
2
h
2
j
2
a
3
b
3
c
3
d
3
e
3
i
3
f
3
g
3
h
3
j
3
UG366_c3_02_051509
TXDATA
TX_DATA_WIDTH = 40
8B/10B
15 14 13 12 11 10 9 8 7 6 5 4 3 210
H
1
G
1
F
1
E
1
D
1
C
1
B
1
A
1
H
0
G
0
F
0
E
0
D
0
C
0
B
0
A
0
H
0
G
0
F
0
E
0
D
0
C
0
B
0
A
0
76543 210
H
3
G
3
F
3
E
3
D
3
C
3
B
3
A
3
TXDATA
H
2
G
2
F
2
E
2
D
2
C
2
B
2
A
2
23 22 21 20 19 18 17 1631 30292827262524
8B/10B
TX_DATA_WIDTH = 10
Transmitted
Last
Transmitted
First
Transmitted
First
Transmitted
Last
a
0
b
0
c
0
d
0
e
0
i
0
f
0
g
0
h
0
j
0
a
1
b
1
c
1
d
1
e
1
i
1
f
1
g
1
h
1
j
1
TX_DATA_WIDTH = 20
8B/10B
15 14 13 1211109876543 210
H
1
G
1
F
1
E
1
D
1
C
1
B
1
A
1
H
0
G
0
F
0
E
0
D
0
C
0
B
0
A
0
TXDATA
Transmitted
First
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English