Xilinx Virtex-6 FPGA User Manual

288 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 5: Board Design Guidelines
layers above and below the power planes. Because of their low impedance, power planes
are often prime candidates for providing return current paths for signals routed above or
below them, even if the path is not intended. The ground planes also provide a means to
connect the ground pins in the GTX transceiver region of the Virtex-6 FPGA.
GTX Transceiver Power Connections
Connections between the GTX power pins and the power distribution network are critical
to the overall transceiver performance. The interface between the power distribution
network and FPGA must be low impedance and low noise. The maximum noise allowed
on the GTX power supplies at the FPGA is 10 mV
PP
from 10 kHz to 80 MHz.
As mentioned in Board Stackup, the GTX transceiver power can be supplied by power
islands.
Figure 5-12 shows the orientation of the power islands to the GTX transceiver region of the
Virtex-6 package pinout. The power islands do not protrude into the SelectIO interface
region of the FPGA.
Figure 5-13 shows how the power islands are oriented under the GTX transceiver region of
the Virtex-6 FPGA and how to avoid exposure to the SelectIO interface region of the
Virtex-6 FPGA BGA pin field. It also shows how filter capacitors discussed in Power
Supply Decoupling Capacitors, page 286 can be oriented on the power planes to provide
adequate noise filtering.
X-Ref Target - Figure 5-12
Figure 5-12: GTX Power Supply Islands
UG366_c5_12_051509
1.0V MGTAVCC Power Island
Transceiver BGA Region
1.2V MGTAVTT Power Island
GND Plane
GND Plane
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English