Xilinx Virtex-6 FPGA User Manual

204 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
RX CDR
Functional Description
The RX Clock Data Recovery (CDR) circuit in each GTX transceiver extracts the recovered
clock and data from an incoming data stream. Figure 4-13 illustrates the architecture of the
CDR block. Clock paths are shown with dotted lines for clarity.
The GTX transceiver employs phase rotator CDR architecture. Incoming data first goes
through receiver equalization stages. The equalized data is captured by an edge and a data
sampler. The data captured by the data sampler is fed to the DFE state machine and the
downstream transceiver blocks.
The CDR state machine uses the data from both the edge and data samplers to determine
the phase of the incoming data stream and to control the phase interpolators (PI). The
phase for the edge sampler is locked to the transition region of the data stream while the
phase of the data sampler is positioned in the middle of the data eye. A third sampler, the
scan sampler, usually uses the same phase as the data sampler and is used by the DFE
block.
X-Ref Target - Figure 4-13
Figure 4-13: CDR Detail
X-Ref Target - Figure 4-14
Figure 4-14: CDR Sampler Positions
UG366_c4_12_051509
Edge
Sampler
Demux
CDR FSM
Data
Sampler
Scan
Sampler
RXP/N
RXEQ
DFE
DFE
FSM
Local
REFCLK
PI (E)
PI (D)
PI (S)
RX
PLL
R XDATA
RXRECCLK
Demux
UG366_c4_13_051509
E
0
E
1
E
2
D
0
D
1
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English