Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 317
UG366 (v2.5) January 17, 2011
GTX RX Latency
GTX RX Latency
Figure C-3 shows a detailed block diagram of the GTX RX. Refer to RX Overview, page 183
for more details on the GTX RX blocks.
Table C-2 defines the latency for the specific functional blocks or group of functional blocks
of the receiver section of the GTX transceiver. The values in the Block Number column
correspond to the circled numbers in Figure C-3.
X-Ref Target - Figure C-3
Figure C-3: GTX RX Block Diagram
FPGA RX
Interface
PLL
RX
Driver
RX
EQ
DFE
RX OOB
SIPO
Polarity
PRBS
Checker
8B/10B
Decoder
RX PIPE
Control
RX Status
Control
RX
Elastic
Buffer
RX
Gear
Box
Comma
Detect
and
Align
UG366_aC_03_011111
RX Serial Clock PMA Parallel Clock (XCLK)
PCS Parallel Clock
(RXUSRCLK)
FPGA Parallel
Clock
(RXUSRCLK2)
From TX Parallel Data
(Near-End PCS
Loopback)
To TX Parallel Data
(Far-End PMA
Loopback)
To TX Parallel Data
(Far-End PCS
Loopback)
2
6
7
8
9
3
4
5
1
Table C-2: GTX RX Latency
Block
Number
Block
Name
RX Latency (RXUSRCLK)
9
FPGA RX
Interface
RX_DATA_WIDTH = 8/10 RX_DATA_WIDTH = 16/20 RX_DATA_WIDTH = 32/40
1.5 cycle 2 cycles 3 cycles
1+2+3+4
PMA +
Interface
4 cycles ± 1 UI
5
Comma
Detect
RXCOMMADETUSE = 0 RXCOMMADETUSE = 1
1 cycle
SHOW_REALIGN_COMMA
= TRUE
SHOW_REALIGN_COMMA
= FALSE
2.5 to 3.5 cycles 2 to 3 cycles
6
8B/10B
Decoder
RXDEC8B10BUSE = 0 RXDEC8B10BUSE = 1
0 cycles 1 cycle
7
RX Elastic
Buffer
RX_BUFFER_USE = FALSE RX_BUFFER_USE = TRUE
0 cycles
1.5 to 2.5 cycles +
(CLK_COR_MIN_LAT/2)
Total RX Latency
Minimum Maximum
6.5 cycles 14 + (CLK_COR_MIN_LAT/2) ± 1 UI cycles
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English