Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 173
UG366 (v2.5) January 17, 2011
TX Configurable Driver
• Pre-cursor and post-cursor transmit pre-emphasis
• Calibrated termination resistors
Ports and Attributes
Table 3-31 defines the TX configurable driver ports.
X-Ref Target - Figure 3-31
Figure 3-31: TX Driver Block Diagram
UG366_c3_19_072309
MGTTXP
MGTTXN
PISO
Pre-Driver
Pre-Emphasis
Pad Driver
Pre-Driver
Main
Pad Driver
Pre-Driver
Post-Emphasis
Pad Driver
TXPREEMPHASIS[3:0]
TXDIFFCTRL[3:0]
TXPOSTEMPHASIS[4:0]
MGTAVTT
nominal
50Ω
nominal
50Ω
TX Serial Clock =
Data Rate / 2
Table 3-31: TX Configurable Driver Ports
Port Dir Clock Domain Description
TXBUFDIFFCTRL[2:0] In Async Pre-driver Swing Control. The default is 3’b100 (nominal
value).
Do not modify this value.
TXDEEMPH In Async TX de-emphasis control for PCI Express PIPE interface. This
signal is mapped internally to TXPOSTEMPHASIS via attributes.
0: 6.0 dB de-emphasis (TX_DEEMPH_0[4:0] attribute)
1: 3.5 dB de-emphasis (TX_DEEMPH_1[4:0] attribute)
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English