Xilinx Virtex-6 FPGA User Manual

130 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 3: Transmitter
These rules about the relationships between clocks must be observed for TXUSRCLK and
TXUSRCLK2:
• TXUSRCLK and TXUSRCLK2 must be positive-edge aligned, with as little skew as
possible between them. As a result, low-skew clock resources (BUFGs and BUFRs)
should be used to drive TXUSRCLK and TXUSRCLK2. Table 3-3 and Table 3-4
describe the appropriate GEN_TXUSRCLK setting and TXUSRCLK2 frequency
requirements. In cases where TXUSRCLK is generated by the user, the designer must
ensure that TXUSRCLK and TXUSRCLK2 are positive-edge aligned.
• Even though they might run at different frequencies, TXUSRCLK, TXUSRCLK2, and
the transmitter reference clock must have the same oscillator as their source. Thus
TXUSRCLK and TXUSRCLK2 must be multiplied or divided versions of the
transmitter reference clock.
Ports and Attributes
Table 3-5 defines the FPGA TX Interface ports.
Table 3-4: TXUSRCLK2 Frequency Relationship to TXUSRCLK
TX_DATA_WIDTH TXUSRCLK2 Frequency
1-Byte 8, 10 F
TXUSRCLK2
= 2 x F
TXUSRCLK
2-Byte 16, 20 F
TXUSRCLK2
= F
TXUSRCLK
4-Byte 32, 40 F
TXUSRCLK2
= F
TXUSRCLK
/ 2
Table 3-5: FPGA TX Interface Ports
Port Dir Clock Domain Description
MGTREFCLKFAB[1:0] Out Clock Reserved. Do not use this port.
TXCHARDISPMODE[3:0] In TXUSRCLK2 When 8B/10B encoding is disabled, TXCHARDISPMODE is used
to extend the data bus for 10- and 20-bit TX interfaces.
TXCHARDISPVAL[3:0] In TXUSRCLK2 When 8B/10B encoding is disabled, TXCHARDISPVAL is used to
extend the data bus for 10- and 20-bit TX interfaces.
TXDATA[31:0] In TXUSRCLK2 The bus for transmitting data. The width of this port depends on
TX_DATA_WIDTH:
TXDATAWIDTH = 8,10: TXDATA[7:0] = 8 bits wide
TXDATAWIDTH = 16,20: TXDATA[15:0] = 16 bits wide
TXDATAWIDTH = 32,40: TXDATA[31:0] = 32 bits wide
When a 10-bit, 20-bit, or 40-bit bus is required, the
TXCHARDISPVAL and TXCHARDISPMODE ports from the
8B/10B encoder are concatenated with the TXDATA port. See
Table 3-2.
TXUSRCLK In Clock This port is used to provide a clock for the internal TX PCS
datapath. In some use cases, this clock is internally generated. See
Table 3-3.
TXUSRCLK2 In Clock This port is used to synchronize the FPGA logic with the TX
interface. This clock must be positive-edge aligned to TXUSRCLK
when TXUSRCLK is provided by the user.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English