Xilinx Virtex-6 FPGA User Manual

274 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 5: Board Design Guidelines
Figure 5-1 shows the connections of the power supply pins for the GTX transceiver. The
listed voltages are nominal values. Refer to the Virtex-6 FPGA Data Sheet for values and
operating conditions.
Termination Resistor Calibration Circuit
One resistor calibration circuit (RCAL) is shared between all of the Quad primitives in a
Quad column (see Figure 5-2). The MGTAVTTRCAL and MGTRREF pins are used to
connect the bias circuit power and the external calibration resistor to the RCAL circuit. The
RCAL circuit performs the resistor calibration only during configuration of the FPGA.
Prior to configuration, all analog supply voltages must be present and within the proper
tolerance as specified in the Virtex-6 FPGA Data Sheet.
The RCAL circuit is associated with the MGT115 Quad. It is referred to as the RCAL
Master. The RCAL Master performs the termination resistor calibration during
configuration of the FPGA and then distributes the calibrated values to all of the Quads in
the column.
MGTRXP0/MGTRXN0
MGTRXP1/MGTRXN1
MGTRXP2/MGTRXN2
MGTRXP3/MGTRXN3
In
(Pad)
RXP and RXN are the differential input pairs for each of the receivers in the Quad.
MGTTXP0/MGTTXN0
MGTTXP1/MGTTXN1
MGTTXP2/MGTTXN2
MGTTXP3/MGTTXN3
Out
(Pad)
TXP and TXN are the differential output pairs for each of the transmitters in the
Quad.
Table 5-1: Quad Pin Descriptions (Cont’d)
Pin Dir Description
X-Ref Target - Figure 5-1
Figure 5-1: Virtex-6 FPGA GTX Transceiver Power Supply Connections
Quad
GTX Column RCAL
MGTAVCC
MGTAVTT
MGTAVTTRCAL
100 ohm
1.2V
1.0V
MGTRREF
UG366_c5_01_051809
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English