Xilinx Virtex-6 FPGA User Manual

154 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 3: Transmitter
Ports and Attributes
Table 3-16 defines the TX buffer ports.
Table 3-16 defines the TX buffer attributes.
Using the TX Buffer
To use the TX buffer to resolve phase differences between the domains, TX_BUFFER_USE
must be set to TRUE. The buffer should be reset whenever TXBUFSTATUS indicates an
overflow or an underflow. The buffer can be reset using GTXTXRESET or TXRESET.
Assertion of GTXTXRESET triggers a sequence that resets the entire TX of the GTX
transceiver.
Using the TX Buffer for Oversampling Mode
When oversampling is enabled (OVERSAMPLE_MODE = TRUE), the TX buffer is used for
bit interpolation and must always be active. See TX Oversampling, page 166 for more
information about built-in 5X oversampling.
Table 3-16: TX Buffer Ports
Port Dir Clock Domain Description
TXBUFSTATUS[1:0] Out TXUSRCLK2 TX buffer status.
TXBUFSTATUS[1]: TX buffer overflow or underflow
1: FIFO has overflowed or underflowed
0: No overflow/underflow error
TXBUFSTATUS[0]: TX buffer fullness
1: FIFO is at least half full
0: FIFO is less than half full
When TXBUFSTATUS[1] goes High, it remains High until TXRESET
is asserted.
TXRESET In Async PCS TX system reset. This input resets the TX FIFO, 8B/10B encoder,
and other transmitter registers. This reset is a subset of
GTXTXRESET.
Table 3-17: TX Buffer Attributes
Attribute Type Description
TX_BUFFER_USE Boolean Use or bypass the TX buffer.
TRUE: Use the TX buffer.
FALSE: Bypass the TX buffer (advanced feature).
TX_OVERSAMPLE_MODE Boolean Enables/disables the built-in 5X digital oversampling.
TRUE: Built-in 5X digital oversampling is enabled. This option is used for
slow line rates.
FALSE: Built-in 5X digital oversampling is disabled. This option is used
for TX normal mode.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English