Xilinx Virtex-6 FPGA User Manual

178 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 3: Transmitter
Use Modes – TX Driver
General
TX_DRIVE_MODE is set to “DIRECT”.
Based on the application requirement, TXDIFFCTRL, TXPREEMPHASIS, and
TXPOSTEMPHASIS values are set to the appropriate values.
PCIe Mode
TX_DRIVE_MODE is set to “PIPE”.
Then the PHY Interface for the PCI Express Architecture, PCI Express 3.0 Document,
Revision 0.5, August 2008 is followed to use the TXMARGIN, TXSWING, and
TXDEEMPH signals. See Table 3-31, page 173 for TXMARGIN, TXSWING, TXDEEMPH,
and TXPOSTEMPHASIS mappings.
Customizable User Presets
TX_DRIVE_MODE is set to “PIPE”.
To make the interface easier to use, the TX_MARGIN_*_*, TX_DEEMPH_* attributes can
be set to the user defaults and then TXSWING, TXMARGIN, and TXDEEMP can be used to
control the TX driver. See Table 3-31, page 173 for TXMARGIN, TXSWING, TXDEEMPH,
and TXPOSTEMPHASIS mappings.
This is used in a backplane situation where the presets (TX_MARGIN_*_*, TXSWING)
correspond to different slot numbers.
Use Mode – Resistor Calibration
For more information on the on-chip resistor calibration, refer to Termination Resistor
Calibration Circuit, page 274.
TX_MARGIN_LOW_2[6:0] 7-bit
Binary
This attribute has the value of TXBUFFDIFFCTRL[2:0] and
TXDIFFCTRL[3:0] that has to be mapped when TXMARGIN = 010 and
TXSWING = 1. TX_MARGIN_LOW_2 = TXBUFDIFFCTRL[2:0],
TXDIFFCTRL[3:0]. The default is 7’b1000010 (290 mV
PPD
typical).
Do not modify this value.
TX_MARGIN_LOW_3[6:0] 7-bit
Binary
This attribute has the value of TXBUFFDIFFCTRL[2:0] and
TXDIFFCTRL[3:0] that has to be mapped when TXMARGIN = 011 and
TXSWING = 1. TX_MARGIN_LOW_3 = TXBUFDIFFCTRL[2:0],
TXDIFFCTRL[3:0]. The default is 7’b1000000 (130 mV
PPD
typical).
Do not modify this value.
TX_MARGIN_LOW_4[6:0] 7-bit
Binary
This attribute has the value of TXBUFFDIFFCTRL[2:0] and
TXDIFFCTRL[3:0] that has to be mapped when TXMARGIN = 100 and
TXSWING = 1. TX_MARGIN_LOW_4 = TXBUFDIFFCTRL[2:0],
TXDIFFCTRL[3:0]. The default is 7’b1000000 (130 mV
PPD
typical).
Do not modify this value.
Table 3-32: TX Configurable Driver Attributes (Cont’d)
Attribute Type Description
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English