Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 235
UG366 (v2.5) January 17, 2011
RX Buffer Bypass
Using the RX Phase Alignment Circuit to Bypass the Buffer
Bypassing the RX buffer is an advanced feature. RX buffer bypass can operate only under
certain system-level conditions. To use the RX phase-alignment circuit, follow these steps:
1. Set the following attributes with their values as follows:
a. Set RXRECCLK_CTRL:
- 2 byte or 4 byte – use RXRECCLKPMA_DIV2
- 1 byte – use RXRECCLKPMA_DIV1
b. Set RX_BUFFER_USE to FALSE to bypass the RX elastic buffer.
c. Set RX_XCLK_SEL to RXUSR.
d. Set RX_DLYALIGN_OVRDSETTING to 8’b10000000.
2. Make sure all the input ports RXENPMAPHASEALIGN and RXPMASETPHASE are
driven Low.
3. Make sure that the ports RXDLYALIGNOVERRIDE and RXDLYALIGNDISABLE are
driven High.
4. Reset the RX datapath using GTXRXRESET or the RXCDRRESET.
5. If an MMCM is used to generate RXUSRCLK/RXUSRCLK2 clocks, wait for the
MMCM to lock.
6. Wait for the CDR to lock and provide a stable RXRECCLK.
7. Assert RXDLYALIGNRESET for 20 RXUSRCLK2 clock cycles.
8. Drive RXENPMAPHASEALIGN High. Keep RXENPMAPHASEALIGN High unless
the phase-alignment procedure must be repeated. Driving RXENPMAPHASEALIGN
Low causes phase align to be lost.
9. Wait 32 RXRUSCLK2 clock cycles and then drive RXPMASETPHASE High for
32 RXUSRCLK2 cycles and then deassert it.
10. Drive RXDLYALIGNDISABLE High.
Step 6 requires careful guidance. Normally, CDR lock is detected by measuring the quality
of incoming data.
RXRECCLK_CTRL String This attribute is the multiplexer select signal from the RX Clock Divider
Control block (see Figure 4-15, page 207).
RXRECCLKPCS (DRP value 000)
RXRECCLKPMA_DIV1 (DRP value 001)
RXRECCLKPMA_DIV2 (DRP value 010)
RXPLLREFCLK_DIV1 (DRP value 011)
RXPLLREFCLK_DIV2 (DRP value 100)
OFF_LOW (DRP value 101)
OFF_HIGH (DRP value 110)
RXUSRCLK_DLY 16-bit
Hex
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
PMA_RXSYNC_CFG 7-bit
Hex
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
Table 4-41: RX Buffer Bypass Attributes (Cont’d)
Attribute Type Description
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English