Xilinx Virtex-6 FPGA User Manual

236 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Figure 4-32 shows the RX phase alignment procedure.
Notes for Figure 4-32.
1. Assert this signal when RXUSRCLK/RXUSRCLK2 clocks are stabilized.
2. Repeat the RXPMASETPHASE procedure if bad data is received (see Figure 4-33)
When the RX elastic buffer is bypassed, data received from the PMA might be distorted
due to phase differences as it passes to the PCS. This makes it difficult to determine
whether or not bad data is received because the CDR is not locked, or the CDR is locked
and the phase alignment has not yet been attempted. To work around this, RX phase
alignment must be repeated multiple times and the output data evaluated after each
attempt. Good data is received if the phase is aligned while the RX CDR is locked. This
process must be repeated until valid data is received at the fabric interface.
The flow diagram in Figure 4-33 shows the series of steps required for successful RX phase
alignment. Any number of clock cycles can be used for the CDR lock time, but using a
larger number decreases the number of cycles through the states.
X-Ref Target - Figure 4-32
Figure 4-32: RX Phase Alignment Procedure
UG366_c4_29_011111
RXENPMAPHASEALIGN
RXPMASETPHASE
RXDLYALIGNRESET
(1)
RXDLYALIGNDISABLE
20 RXUSRCLK2 cycles
32 RXUSRCLK2 cycles
32 RXUSRCLK2 cycles
(2)
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English