Xilinx Virtex-6 FPGA

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 237
UG366 (v2.5) January 17, 2011
RX Buffer Bypass
X-Ref Target - Figure 4-33
Figure 4-33: Steps Required for Successful RX Phase Alignment
Assert RXPMASETPHASE
for 32 RXUSRCLK2 Cycles
to Phase Align
Wait for MMCM Lock.
RXN/RXP Should be Driven.
Fail
UG366_c4_30_122810
Pass
Phase Alignment
Done
RESET
Validate Data
Received at
Fabric Interface
Drive
RXENPMAPHASEALIGN
and Wait for 32
RXUSRCLK2 Cycles
www.BDTIC.com/XILINX