Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 227
UG366 (v2.5) January 17, 2011
RX Loss-of-Sync State Machine
LOSS_OF_SYNC state. The RX_LOS_THRESHOLD entry in Table 4-37 shows the valid
settings for this attribute.
The LOS state machine allows the error count in the SYNC_ACQUIRED state to decrease
over time, so that sparse errors are eventually discarded. The rate that the error count is
decreased is controlled by the RX_LOS_THRESHOLD and RX_LOS_INVALID_INCR
attributes, as defined in Table 4-37.
Ports and Attributes
Table 4-36 defines the RX Loss-of-Sync State Machine ports.
Table 4-37 defines the RX Loss-of-Sync State Machine attributes.
Table 4-36: RX Loss-Of-Sync State Machine Ports
Port Dir Clock Domain Description
RXLOSSOFSYNC Out RXUSRCLK2 FPGA status related to byte stream synchronization. The meaning
depends on the state of the RX_LOSS_OF_SYNC_FSM attribute.
If RX_LOSS_OF_SYNC_FSM = TRUE, this output reflects the state
of an internal Loss-of-Sync FSM as follows:
[1] = 1: Sync lost due to either sequence of invalid characters or
reset
[0] = 1: In the resync state due to a channel bonding sequence or
realignment
If RX_LOSS_OF_SYNC_FSM = FALSE, this output presents the
following information about incoming data:
[1] = 1: Received data is not an 8B/10B character or has a disparity
error
[0] = 1: Channel bonding sequence detected in data
Table 4-37: RX Loss-Of-Sync State Machine Attributes
Attribute Type Description
RX_LOS_INVALID_INCR Integer Defines the number of valid characters required to cancel out the appearance of
one invalid character for the purpose of loss-of-sync determination. Valid
settings are 1, 2, 4, 8, 16, 32, 64, and 128.
RX_LOS_THRESHOLD Integer When divided by RX_LOS_INVALID_INCR, defines the number of invalid
characters required to cause an FSM transition to the sync lost state. Valid
settings are 4, 8, 16, 32, 64, 128, 256, and 512.
RX_LOSS_OF_SYNC_FSM Integer RX_LOSS_OF_SYNC_FSM defines the behavior of the RXLOSSOFSYNC[1:0]
outputs.
FALSE (default): RXLOSSOFSYNC[1] goes High when invalid data (not in
table or disparity error) is found in 8B/10B decoding. RXLOSSOFSYNC[0]
goes High when a channel bonding sequence has been written into the RX
elastic buffer.
TRUE: Loss of sync FSM is in operation and its state is reflected on
RXLOSSOFSYNC[1].
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English