Xilinx Virtex-6 FPGA User Manual

128 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 3: Transmitter
8. TX Oversampling, page 166
9. TX Polarity Control, page 166
10. TX Fabric Clock Output Control, page 167
11. TX Configurable Driver, page 172
12. TX Receiver Detect Support for PCI Express Designs, page 179
13. TX Out-of-Band Signaling, page 180
FPGA TX Interface
Functional Description
The FPGA TX interface is the FPGA’s gateway to the TX datapath of the GTX transceiver.
Applications transmit data through the GTX transceiver by writing data to the TXDATA
port on the positive edge of TXUSRCLK2. The width of the port can be configured to be
one, two, or four bytes wide. The actual width of the port depends on the
TX_DATA_WIDTH attribute and TXENC8B10BUSE port settings. Port widths can be 8, 10,
16, 20, 32, and 40 bits.
The rate of the parallel clock (TXUSRCLK2) at the interface is determined by the TX line
rate, the width of the TXDATA port, and whether or not 8B/10B encoding is enabled. In
some operating modes, a second parallel clock (TXUSRCLK) must be provided for the
internal PCS logic in the transmitter. This section shows how to drive the parallel clocks
and explains the constraints on those clocks for correct operation. The highest transmitter
data rates require a 4-byte interface to achieve a TXUSRCLK2 rate in the specified
operating range.
Interface Width Configuration
The Virtex®-6 FPGA GTX transceiver contains an internal 2-byte datapath. The FPGA
interface width is configurable by setting the TX_DATA_WIDTH attribute. When the
8B/10B encoder is enabled, the FPGA interface must be configured to 10 bits, 20 bits, or
40 bits. When the 8B/10B encoder is bypassed, the FPGA interface is configured to any of
the available widths: 8, 10, 16, 20, 32, or 40 bits. Table 3-1 shows how the interface width for
the TX datapath is selected. 8B/10B encoding is described in more detail in TX 8B/10B
Encoder, page 143.
Table 3-1: FPGA TX Interface Datapath Configuration
TXENC8B10BUSE TX_DATA_WIDTH FPGA Interface Width Internal Data Width
1 10 8 bits 20 bits
20 16 bits 20 bits
40 32 bits 20 bits
0 8 8 bits 16 bits
10 10 bits 20 bits
16 16 bits 16 bits
20 20 bits 20 bits
32 32 bits 16 bits
40 40 bits 20 bits
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English