Xilinx Virtex-6 FPGA User Manual

234 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Table 4-41 defines the RX buffer bypass attributes.
Table 4-41: RX Buffer Bypass Attributes
Attribute Type Description
POWER_SAVE 10-bit
Binary
POWER_SAVE[4]:
Mux select for the TXOUTCLK output clock. Must be tied to 1’b1.
1'b0: Use the TX Delay Aligner
1'b1: Bypass the TX Delay Aligner
POWER_SAVE[5]:
Mux select for the RXRECCLK output clock. Must be tied to 1’b1 when
RX buffer is used (RX_BUFFER_USE = TRUE). When RX buffer is
bypassed, refer to Using the RX Phase Alignment Circuit to Bypass the
Buffer, page 235.
1'b0: Use the RX Delay Aligner
1'b1: Bypass the RX Delay Aligner
All other bits are reserved. Use recommended values from the Virtex-6
FPGA GTX Transceiver Wizard.
RX_BUFFER_USE Boolean Use or bypass the RX elastic buffer.
TRUE: Use the RX elastic buffer (normal mode).
FALSE: Permanently bypass the RX elastic buffer (advanced feature).
RX_DATA_WIDTH Integer Sets the receiver external data width.
8/10: 1 byte interface
16/20: 2 byte interface
32/40: 4 byte interface
If 8B10B is used, this attribute must be a multiple of 10.
RX_DLYALIGN_CTRINC 4-bit
Binary
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
RX_DLYALIGN_EDGESET 5-bit
Binary
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
RX_DLYALIGN_LPFINC 4-bit
Binary
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
RX_DLYALIGN_MONSEL 3-bit
Binary
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
RX_DLYALIGN_OVRDSETTING 8-bit
Binary
Sets the overdrive value for the RX delay aligner. This attribute takes
effect when RXDLYALIGNOVERRIDE is driven High. This attribute
must be set to 8’b10000000.
RX_XCLK_SEL String Selects the clock used to drive the RX parallel clock domain (XCLK).
“RXREC”: (default) XCLK domain driven by recovered clock from
CDR. When OVERSAMPLE_MODE is TRUE, the recovered clock is
sourced from the oversampling block.
“RXUSR”: RXUSRCLK port drives RX parallel clock domain. Use
this mode when bypassing the RX elastic buffer.
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English