Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 137
UG366 (v2.5) January 17, 2011
TX Initialization
All reset ports described in this section initiate the internal transmitter state machines
when driven High. The internal reset state machines are held in the reset state until these
same reset ports are driven Low. The completion of these state machines is signaled
through the TXRESETDONE port.
Figure 3-8 shows the GTX TX reset hierarchy.
When bypassing the TX buffer, GTXTXRESET, GTXRXRESET, PLLTXRESET, and
PLLRXRESET must not be tied High. Refer to TX Buffer Bypass, page 155 for more
information.
The GTX TX can use either TX PLL or RX PLL. Whichever PLL is used, if
TXPLL_DIVSEL_OUT is set to /2 or /4, the TX output clock divider must be reset twice
when the associated PLLLKDET signal goes from Low to High. Resetting the TX output
clock divider twice (double reset) is achieved through the GTXTEST[1] port, and is
required under these conditions:
• When the TX output clock divider, TXPLL_DIVSEL_OUT, is set to /2 or /4
• After FPGA power-up and configuration
• After the associated reset of the PLL used by the TX is toggled
• After turning on a reference clock to the PLL used by the TX
• After changing the reference clock to the PLL used by the TX
• After assertion/deassertion of TXPOWERDOWN
• After assertion/deassertion of GTXTXRESET
The circuit that implements the double reset through GTXTEST[1] must use a free running
clock. This clock can be sourced from:
• IBUFDS output. This also provides the MGTREFCLK to the GTX transceiver.
•DRP clock.
• Any other free running clock from the user design.
The circuit must follow the timing diagram shown in Figure 3-9.
X-Ref Target - Figure 3-8
Figure 3-8: GTX TX Reset Hierarchy
X-Ref Target - Figure 3-9
Figure 3-9: Transmitter Reset After Configuration
After Configuration or GTXTXRESET or
Falling TXPLLPOWERDOWN
PLLTXRESET TXRESET
UG366_c3_27_061109
CLK
GTXTEST[1]
TXPLLLKDET /
RXPLLLKDET
UG366_c3_33_092410
1024
CLKs
256
CLKs
256
CLKs
256
CLKs
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Xilinx Virtex-6 FPGA Specifications

General

Technology	40nm
Clock Data Recovery (CDR)	Integrated
Logic Cells	Up to 760, 000
I/O Pins	Up to 1200
Transceiver Features	Pre-emphasis, equalization
Transceiver Protocol Support	PCIe, SATA, Ethernet, CPRI, OBSAI, Serial RapidIO
Power Consumption	Varies by model and configuration
Transceiver Type	Multi-Gigabit Transceivers (RocketIO GTP/GTX)

Summary

Preface: About This Guide

Guide Contents

Lists the chapters and appendices included in this manual.

Additional Documentation

Provides links to other Xilinx documents for further information.

Chapter 1: Transceiver and Tool Overview

Overview

Introduces the Virtex-6 FPGA GTX transceiver and its features.

Port and Attribute Summary

Summarizes GTX ports and attributes, grouped by functionality.

Simulation

Explains prerequisites and setup for simulating GTX transceiver designs.

Implementation

Details mapping GTX transceivers to device resources and UCF creation.

Chapter 2: Shared Transceiver Features

Reference Clock Input Structure

Describes the structure and ports for reference clock inputs.

Reference Clock Selection

Explains how to select and route reference clocks for GTX transceivers.

PLL

Details the Phase-Locked Loop (PLL) architecture and its settings.

Power Down

Describes the various power-down modes and capabilities of the GTX transceiver.

Loopback

Explains loopback modes for testing the transceiver datapath.

ACJTAG

Covers the ACJTAG interface support for GTX transceivers.

Dynamic Reconfiguration Port

Explains the DRP for dynamic parameter changes in GTXE1 primitive.

Chapter 3: Transmitter

TX Overview

Introduces the functional blocks and key elements of the GTX transmitter.

FPGA TX Interface

Describes the gateway for transmitting data to the GTX transceiver.

TX Initialization

Details the procedures for resetting and initializing the GTX TX.

TX 8B/10B Encoder

Explains the 8B/10B encoding scheme used for outgoing data.

TX Gearbox

Describes support for 64B/66B and 64B/67B encoding for high-speed protocols.

TX Buffer

Explains the TX buffer's role in resolving phase differences between domains.

TX Buffer Bypass

Covers the advanced feature of bypassing the TX buffer for reduced latency.

TX Pattern Generator

Details the PRBS and other patterns for testing signal integrity.

TX Oversampling

Explains the built-in 5X oversampling feature for serial rates.

TX Polarity Control

Describes the function to invert outgoing data polarity before transmission.

TX Fabric Clock Output Control

Details the serial and parallel clock divider control for TX fabric clocks.

TX Configurable Driver

Explains the high-speed current-mode differential output buffer features.

TX Receiver Detect Support for PCI Express Designs

Describes the feature for detecting receiver presence on a link.

TX Out-of-Band Signaling

Covers support for SATA/SAS OOB sequences and PCI Express beaconing.

Chapter 4: Receiver

RX Overview

Introduces the functional blocks and key elements of the GTX receiver.

RX Analog Front End

Describes the high-speed current-mode input differential buffer.

RX Out-of-Band Signaling

Covers support for decoding SATA/SAS OOB sequences and PCI Express beacons.

RX Equalizer

Explains the circuit for compensating high-frequency losses in the channel.

RX CDR

Details the Clock Data Recovery circuit for extracting clock and data.

RX Fabric Clock Output Control

Covers serial and parallel clock divider control for RX fabric clocks.

RX Margin Analysis

Discusses methods for determining link quality via eye diagrams.

RX Polarity Control

Describes the function to invert incoming data polarity.

RX Oversampling

Explains the built-in 5X oversampling for low serial rates.

RX Pattern Checker

Details the built-in PRBS checker for testing channel signal integrity.

RX Byte and Word Alignment

Explains the process of aligning serial data to byte boundaries.

RX Loss-of-Sync State Machine

Describes the state machine for detecting channel malfunction.

RX 8B/10B Decoder

Explains the decoder for RX data, indicating errors and control sequences.

RX Buffer Bypass

Covers the advanced feature of bypassing the RX elastic buffer for low latency.

RX Elastic Buffer

Explains the buffer for resolving clock domain differences.

RX Clock Correction

Details the circuit for tolerating frequency differences between clock domains.

RX Channel Bonding

Describes using the RX elastic buffer to cancel skew between lanes.

RX Gearbox

Describes support for 64B/66B and 64B/67B encoding for high-speed protocols.

RX Initialization

Details the procedures for resetting and initializing the GTX RX.

FPGA RX Interface

Describes the interface for receiving RX data from the GTX RX.

Chapter 5: Board Design Guidelines

Overview

Discusses implementing GTX transceivers on a PCB for optimal performance.

Pin Description and Design Guidelines

Describes GTX transceiver pins and provides design guidelines.

Termination Resistor Calibration Circuit

Explains the circuit for calibrating termination resistors.

Analog Power Supply Pins

Details the MGTAVCC and MGTAVTT analog power supply pins.

Reference Clock

Focuses on the selection criteria for reference clock sources.

Power Supply Distribution Network

Discusses issues regarding power supply implementation on the PCB.

Crosstalk

Explains how crosstalk degrades GTX transceiver performance and how to avoid it.

SelectIO Usage Guidelines

Provides guidelines for SelectIO interface usage to minimize GTX impact.