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Xilinx Virtex-6 FPGA User Manual

Xilinx Virtex-6 FPGA
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Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 265
UG366 (v2.5) January 17, 2011
RX Initialization
Table 4-55 lists the recommended resets for various situations.
Table 4-54: Available Receiver Resets and the Components Reset by Them
Component Configuration
GTXRXRESET
RXPLLPOWERDOWN (Falling Edge)
PLLRXRESET
RXCDRRESET
RXRESET
RXBUFRESET
PRBSCNTRESET
RXDLYALIGNRESET
RX PCS
FPGA RX
Interface
** **
RX Gearbox * ** **
RX Status
Control
*****
RX Elastic
Buffer
* ** ***
8B/10B
Decoder
*****
Comma Detect
and Align
*****
RX LOS State
Machine
*****
RX Polarity * * * * *
PRBS Checker * ** ** *
5X
Oversampler
*****
RX Delay
Aligner
**
RX PMA
RX Analog
Front End
***
RX OOB * * * *
RX Equalizer * * *
RX PLL * ***
RX CDR * * * *
SIPO * * * *
Loopback
Loopback
Paths
***
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Xilinx Virtex-6 FPGA Specifications

General IconGeneral
BrandXilinx
ModelVirtex-6 FPGA
CategoryTransceiver
LanguageEnglish

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