Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 111
UG366 (v2.5) January 17, 2011
Reference Clock Selection
Note: The IBUFDS_GTXE1 diagram in Figure 2-6 is a simplification. The output port ODIV2 is left
floating, and the input port CEB is set to logic 0.
The User Constraints File (UCF) can be used to constrain the location of the transceivers
and the corresponding reference clock source location. For example, if Q(n) in Figure 2-6
belongs to QUAD_114 of an LX75T-FF484 device (as shown in Figure 1-6, page 43), these
constraints can be applied:
## Set placement for the corresponding GTXE1 instances
INST rocketio_wrapper_i/gtx0_rocketio_wrapper_i/gtxe1_i LOC=GTXE1_X0Y0;
INST rocketio_wrapper_i/gtx1_rocketio_wrapper_i/gtxe1_i LOC=GTXE1_X0Y1;
INST rocketio_wrapper_i/gtx2_rocketio_wrapper_i/gtxe1_i LOC=GTXE1_X0Y2;
INST rocketio_wrapper_i/gtx3_rocketio_wrapper_i/gtxe1_i LOC=GTXE1_X0Y3;
## Reference clock constraints. Assign the IBUFDS_GTXE1 input nets to the
## package pins for the corresponding dedicated clock sources
## MGTREFCLK0[P/N]_114 or MGTREFCLK1[P/N]_114.
NET MGTREFCLK0N LOC=U3;
NET MGTREFCLK0P LOC=U4;
NET MGTREFCLK1N LOC=R3;
NET MGTREFCLK1N LOC=R4;
Figure 2-6 shows that the TX PLL and RX PLL of each transceiver can be sourced by either
MGTREFCLK0[P/N] or MGTREFCLK1[P/N]. Users can set TXPLLREFSELDY[2:0] and
RXPLLREFSELDY[2:0] to the corresponding value as shown in Figure 2-3, page 105.
X-Ref Target - Figure 2-6
Figure 2-6: Multiple GTX Transceivers with Multiple Reference Clocks
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLK0P
MGTREFCLK0N
I
IB
O
MGTREFCLK1P
MGTREFCLK1N
UG366_c2_08_081109
I
IB
O
MGTREFCLKTX[1]
MGTREFCLKRX[1]
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
MGTREFCLKTX[0]
MGTREFCLKRX[0]
MGTREFCLKTX[1]
MGTREFCLKRX[1]
GTXE1
GTXE1
GTXE1
GTXE1
Q
(n)
IBUFDS_GTXE1
IBUFDS_GTXE1
www.BDTIC.com/XILINX

Xilinx Virtex-6 FPGA Specifications

General

Technology	40nm
Clock Data Recovery (CDR)	Integrated
Logic Cells	Up to 760, 000
I/O Pins	Up to 1200
Transceiver Features	Pre-emphasis, equalization
Transceiver Protocol Support	PCIe, SATA, Ethernet, CPRI, OBSAI, Serial RapidIO
Power Consumption	Varies by model and configuration
Transceiver Type	Multi-Gigabit Transceivers (RocketIO GTP/GTX)

Summary

Preface: About This Guide

Guide Contents

Lists the chapters and appendices included in this manual.

Additional Documentation

Provides links to other Xilinx documents for further information.

Chapter 1: Transceiver and Tool Overview

Overview

Introduces the Virtex-6 FPGA GTX transceiver and its features.

Port and Attribute Summary

Summarizes GTX ports and attributes, grouped by functionality.

Simulation

Explains prerequisites and setup for simulating GTX transceiver designs.

Implementation

Details mapping GTX transceivers to device resources and UCF creation.

Chapter 2: Shared Transceiver Features

Reference Clock Input Structure

Describes the structure and ports for reference clock inputs.

Reference Clock Selection

Explains how to select and route reference clocks for GTX transceivers.

PLL

Details the Phase-Locked Loop (PLL) architecture and its settings.

Power Down

Describes the various power-down modes and capabilities of the GTX transceiver.

Loopback

Explains loopback modes for testing the transceiver datapath.

ACJTAG

Covers the ACJTAG interface support for GTX transceivers.

Dynamic Reconfiguration Port

Explains the DRP for dynamic parameter changes in GTXE1 primitive.

Chapter 3: Transmitter

TX Overview

Introduces the functional blocks and key elements of the GTX transmitter.

FPGA TX Interface

Describes the gateway for transmitting data to the GTX transceiver.

TX Initialization

Details the procedures for resetting and initializing the GTX TX.

TX 8B/10B Encoder

Explains the 8B/10B encoding scheme used for outgoing data.

TX Gearbox

Describes support for 64B/66B and 64B/67B encoding for high-speed protocols.

TX Buffer

Explains the TX buffer's role in resolving phase differences between domains.

TX Buffer Bypass

Covers the advanced feature of bypassing the TX buffer for reduced latency.

TX Pattern Generator

Details the PRBS and other patterns for testing signal integrity.

TX Oversampling

Explains the built-in 5X oversampling feature for serial rates.

TX Polarity Control

Describes the function to invert outgoing data polarity before transmission.

TX Fabric Clock Output Control

Details the serial and parallel clock divider control for TX fabric clocks.

TX Configurable Driver

Explains the high-speed current-mode differential output buffer features.

TX Receiver Detect Support for PCI Express Designs

Describes the feature for detecting receiver presence on a link.

TX Out-of-Band Signaling

Covers support for SATA/SAS OOB sequences and PCI Express beaconing.

Chapter 4: Receiver

RX Overview

Introduces the functional blocks and key elements of the GTX receiver.

RX Analog Front End

Describes the high-speed current-mode input differential buffer.

RX Out-of-Band Signaling

Covers support for decoding SATA/SAS OOB sequences and PCI Express beacons.

RX Equalizer

Explains the circuit for compensating high-frequency losses in the channel.

RX CDR

Details the Clock Data Recovery circuit for extracting clock and data.

RX Fabric Clock Output Control

Covers serial and parallel clock divider control for RX fabric clocks.

RX Margin Analysis

Discusses methods for determining link quality via eye diagrams.

RX Polarity Control

Describes the function to invert incoming data polarity.

RX Oversampling

Explains the built-in 5X oversampling for low serial rates.

RX Pattern Checker

Details the built-in PRBS checker for testing channel signal integrity.

RX Byte and Word Alignment

Explains the process of aligning serial data to byte boundaries.

RX Loss-of-Sync State Machine

Describes the state machine for detecting channel malfunction.

RX 8B/10B Decoder

Explains the decoder for RX data, indicating errors and control sequences.

RX Buffer Bypass

Covers the advanced feature of bypassing the RX elastic buffer for low latency.

RX Elastic Buffer

Explains the buffer for resolving clock domain differences.

RX Clock Correction

Details the circuit for tolerating frequency differences between clock domains.

RX Channel Bonding

Describes using the RX elastic buffer to cancel skew between lanes.

RX Gearbox

Describes support for 64B/66B and 64B/67B encoding for high-speed protocols.

RX Initialization

Details the procedures for resetting and initializing the GTX RX.

FPGA RX Interface

Describes the interface for receiving RX data from the GTX RX.

Chapter 5: Board Design Guidelines

Overview

Discusses implementing GTX transceivers on a PCB for optimal performance.

Pin Description and Design Guidelines

Describes GTX transceiver pins and provides design guidelines.

Termination Resistor Calibration Circuit

Explains the circuit for calibrating termination resistors.

Analog Power Supply Pins

Details the MGTAVCC and MGTAVTT analog power supply pins.

Reference Clock

Focuses on the selection criteria for reference clock sources.

Power Supply Distribution Network

Discusses issues regarding power supply implementation on the PCB.

Crosstalk

Explains how crosstalk degrades GTX transceiver performance and how to avoid it.

SelectIO Usage Guidelines

Provides guidelines for SelectIO interface usage to minimize GTX impact.