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Xilinx Virtex-6 FPGA User Manual

Xilinx Virtex-6 FPGA
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Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 43
UG366 (v2.5) January 17, 2011
Implementation
X-Ref Target - Figure 1-6
Figure 1-6: Placement Diagram for the FF484 Package (2 of 2)
LX75T: GTXE1_X0Y3
LX130T: GTXE1_X0Y11
LX75T: GTXE1_X0Y2
LX130T: GTXE1_X0Y10
QUAD_114
LX75T: GTXE1_X0Y1
LX130T: GTXE1_X0Y9
LX75T: GTXE1_X0Y0
LX130T: GTXE1_X0Y8
W3
W4
M1
M2
Y1
Y2
P1
P2
R4
R3
U4
U3
AA3
AA4
T1
T2
AB1
AB2
V1
V2
MGTRXP3_114
MGTRXN3_114
MGTTXP3_114
MGTTXN3_114
MGTRXP2_114
MGTRXN2_114
MGTTXP2_114
MGTTXN2_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTRXP1_114
MGTRXN1_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTTXP0_114
MGTTXN0_114
UG366_c1_06_051509
www.BDTIC.com/XILINX

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Xilinx Virtex-6 FPGA Specifications

General IconGeneral
BrandXilinx
ModelVirtex-6 FPGA
CategoryTransceiver
LanguageEnglish

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