Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 253
UG366 (v2.5) January 17, 2011
RX Channel Bonding
As long as timing constraints are met, the following items apply:
• There is no limit to the number of GTX transceivers that can be on a particular
RXCHANBONDLEVEL[2:0].
• GTX transceivers can be on the same RXCHANBONDLEVEL[2:0].
Figure 4-41 shows an example for channel bonding 16 GTX transceivers. This example is
only one of many ways to channel bond 16 GTX transceivers. In this example, transceivers
of the X0 column are channel bonded together.
X-Ref Target - Figure 4-41
Figure 4-41: Channel Bonding Example Using 16 GTX Transceivers
RXCHBONDI
RXCHBONDO
GTX Transceiver
RXCHBONDI
RXCHBONDO
GTX Transceiver
RXCHBONDI
RXCHBONDO
GTX Transceiver
RXCHBONDI
RXCHBONDO
GTX Transceiver
RXCHBONDI
RXCHBONDO
GTX Transceiver
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y9
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y6
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y8
UG366_c4_38_051509
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y7
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y4
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y5
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y2
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y3
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y0
RXCHBONDI
RXCHBONDO
GTX Transceiver
GTXE1_X0Y1
RXCHBONDI
GTX Transceiver
RXCHBONDO
GTXE1_X0Y10
GTXE1_X0Y11
GTXE1_X0Y12 GTXE1_X0Y13
GTXE1_X0Y14
GTXE1_X0Y15
RXCHANBONDSLAVE = 1
RXCHANBONDLEVEL[2:0] = 3
RXCHANBONDSLAVE = 1
RXCHANBONDLEVEL[2:0] = 2
RXCHANBONDSLAVE = 1
RXCHANBONDLEVEL[2:0] = 1
RXCHANBONDSLAVE = 1
RXCHANBONDLEVEL[2:0] = 0
RXCHANBONDMASTER = 1
RXCHANBONDLEVEL[2:0] = 4
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English