Altera Stratix - Page 252

5–72 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Figure 5–45. SERDES Bypass LVDS Receiver Using M512 RAM Block as the Deserializer
Figure 5–46. SERDES Bypass LVDS Transmitter Using M512 RAM Block as Deserializer
datain[0]
inclock
dataout_h[0]
dataout_l[0]
DDIO In
datain[1..0]
waddr[7..0]
wclock
rclock
raddr[5..0]
dataout[7..0]
Simple Dual Port
RX_SESB
512 Bits
inclock ÷1 clock1
÷2 clock0
RX_PLL
RXp
RXn
rx_inclk
W-UpCounter
clock q[4..0]
R-UpCounter
clock q[2..0]
waddr[7..5]
Core data
Core clock
raddr[5..3]
datain[7..0]
waddr[5..0]
wclock
rclock
raddr[7..0]
dataout[7..0]
Simple Dual Port ×2×8
TX_SESB
512 Bits
inclock ÷1 clock1
×2 clock0
RX_PLL
datain_h[0]
datain_l[0]
outclock
datain_h[0]
datain_l[0]
outclock
dataout_h[0]
dataout_l[0]
DDIO Out
/1 clock1
/2 clock0
RX_PLL
core_clk
core_data
W-UpCounter
clock q[2..0]
R-UpCounter
clock q[5..0]
waddr[7..5]
raddr[5..3]
V
CC
GND
TXp
TXn
tx_outclk