Altera Stratix - Page 253

Altera Corporation 5–73
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
For the transmitter, the read counter is the fast counter and the write
counter is the slow counter. For the receiver, the write counter is the fast
counter and the read counter is the slow counter. Tables 5–18 and 5–19
provide the address counter configurations for the transmitter and the
receiver, respectively.
In different M512 memory configurations, the counter width is smaller
than the address width, so you must ground some of the most significant
address bits. Table 5–20 summarizes the address width, the counter
width, and the number of bits to be grounded.
Table 5–18. Address Counters for SERDES Bypass LVDS Receiver
M512 Mode
Deserialization
Factor
Write Up-Counter
(Fast Counter)
Read Up-Counter
(Slow Counter)
Invalid Initial Cycles
Width Starts at Width Starts at Write Read
×2×4 4 4032126
×2×8 8 5032246
×4×16 8 5032246
×2×16 16 6032486
Table 5–19. Address Counters for SERDES Bypass LVDS Transmitter
M512 Mode
Deserialization
Factor
Write Up-Counter
(Fast Counter)
Read Up-Counter
(Slow Counter)
Invalid Initial Cycles
Width Starts at Width Starts at Write Read
×2×4 4 403224
×2×8 8 503228
×4×16 8 503228
×2×16 16 6032216
Table 5–20. Address & Counter Width
M512 Mode
Write Counter
Width
Read Counter
Width
Write Address
Width
Read Address
Width
Number of Grounded Bits
Write Address Read Address
×2×4 438744
×2×8 538633
×4×16637512
×2×16538532