6–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Architecture
Multiplier Stage
The multiplier stage supports 9 × 9, 18 × 18, or 36 × 36 multiplication.
(The multiplier stage also support smaller multipliers. See “Operational
Modes” on page 6–18 for details.) Based on the data width, a single DSP
block can perform many multiplications in parallel.
The multiplier operands can be signed or unsigned numbers. Two
signals, signa and signb, indicate the representation of the two
operands. For example, a logic 1 on the signa signal indicates that data
A is a signed number; a logic 0 indicates an unsigned number. The result
of the multiplication is signed if any one of the operands is a signed
number, as shown in Table 6–3.
The signa and signb signals affect the entire DSP block. Therefore, all
of the data A inputs feeding the same DSP block must have the same sign
representation. Similarly, all of the data B inputs feeding the same DSP
block must have the same sign representation. The multiplier offers full
precision regardless of the sign representation.
1 By default, the Altera Quartus
®
II software sets the multiplier to
perform unsigned multiplication when the signa and signb
signals are not used.
Pipeline Registers
The output from the multiplier can feed a pipeline register or be
bypassed. You can use pipeline registers for any multiplier size;
pipelining is useful for increasing the DSP block performance,
particularly when using subsequent adder stages.
1 In the DSP block, pipelining improves the performance of
36 × 36 multipliers. For 18 × 18 multipliers and smaller,
pipelining adds latency but does not improve performance.
Table 6–3. Multiplier Signed Representation
Data A Data B Result
Unsigned Unsigned Unsigned
Unsigned Signed Signed
Signed Unsigned Signed
Signed Signed Signed
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