Altera Stratix - Page 309

Altera Corporation 7–23
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–13. Implementation of the Polyphase Interpolation Filter (I=4) Notes (1), (2), (3)
Notes to Figure 7–13:
(1) The 1× clock feeds the input data shiftin register chain.
(2) The 4× clock feeds the input registers for the filter coefficients and other optional registers in the DSP block. See
Note (3).
(3) To increase the DSP block performance, include the pipeline, and output registers. See Figure 7–3 for the details.
h
(
0
)
h
(
1
)
h
(
2
)
h
(
3
)
Filter output
y(n)
Note (2)
Clock input
(1x clock)
1x clock
PLL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
4x clock
Note (1)
x
(n)
x
x
DSP block
Data input
RAM
/
R
O
M
0
RAM
/
R
O
M
1
RAM
/
R
O
M
2
RAM
/
ROM
3
Filt
e
r
c
o
e
ffi
c
i
e
nt
s