Altera Stratix - Page 319

Altera Corporation 7–33
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
f For more information on the different modes of the DSP blocks, see the
DSP Blocks in Stratix & Stratix GX Devices chapter.
Figure 7–19 shows an example of a 2-tap complex FIR filter design with
18-bit inputs. The real and the complex outputs of the DSP blocks are
added externally to generate the overall real and imaginary output. As in
the case of basic, TDM, or polyphase FIR filters, the coefficients may be
loaded in series or parallel.
Figure 7–19. 2-Tap 18-Bit Complex FIR Filter Implementation
DSP block
Configured as a subtractor
h
imag1
h
real1
x
imag1
x
real1
out
real1
= x
real1 *
h
real1
- x
imag1 *
h
imag1
out
imag1
= x
real1 *
h
imag1
+ x
imag1 *
h
real1
Configured as a adder
DSP block
Configured as a subtractor
h
imag2
h
real2
x
imag2
x
real2
out
real2
= x
real2 *
h
real2
- x
imag2 *
h
imag2
out
imag2
= x
real2 *
h
imag2
+ x
imag2 *
h
real2
Configured as a adder
Overall real output
Overall imaginary output