Altera Stratix - Page 63

Altera Corporation 1–45
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
RCLK6
vv
RCLK7
vv
RCLK8
vv v
RCLK9
vv v
RCLK10
vv
RCLK11
vv
RCLK12
vv
RCLK13
vv
RCLK14
vv v
RCLK15
vv v
External Clock Output
PLL5_OUT
[3..0]p/n
v
PLL6_OUT
[3..0]p/n
v
PLL11_OUT
(3)
v
PLL12_OUT
(4)
v
Notes to Table 1–15:
(1) This is a fast PLL.
(2) This is an enhanced PLL.
(3) This pin is a tri-purpose pin; it can be an I/O pin, CLK13n, or used for PLL 11 output.
(4) This pin is a tri-purpose pin; it can be an I/O pin, CLK7n, or used for PLL 12 output.
(5) The EP1S40 device in the F780 package does not support PLLs 11 and 12.
Table 1–15. Stratix Global & Regional Clock Output Line Sharing for Enhanced & Fast PLLs (Part 2 of 2)
Clock
Network
All Devices
EP1S30, EP1S40, EP1S60 &
EP1S80 Devices Only
EP1S40 (5),
EP1S60 &
EP1S80
Devices Only
PLL 1
(1)
PLL 2
(1)
PLL 3
(1)
PLL 4
(1)
PLL 5
(2)
PLL 6
(2)
PLL 7
(1)
PLL 8
(1)
PLL
9 (1)
PLL
10 (1)
PLL
11 (2)
PLL
12 (2)