Altera Stratix - Page 72

1–54 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Board Layout
Figure 1–25. External Clock Output Pin Association to Output Power Note (1)
Note to Figure 1–25:
(1) These pins apply to PLL 5. The figure for PLL 6 is similar, except that the pin names
begin with the prefix PLL6 instead of PLL5.
PLL5_OUT0p
VCC_PLL5_OUTA
PLL5_OUT0n
PLL5_OUT0p
PLL5_OUT0n
PLL5_OUT2p
VCC_PLL5_OUTB
PLL5_OUT2n
PLL5_OUT3p
PLL5_OUT3n