Altera Stratix - Page 9

Altera Corporation ix
Contents Contents
Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Introduction ............................................................................................................................................ 8–1
Related Links ..................................................................................................................................... 8–1
10-Gigabit Ethernet ................................................................................................................................ 8–1
Interfaces ................................................................................................................................................. 8–5
XSBI .................................................................................................................................................... 8–5
XGMII ............................................................................................................................................... 8–13
XAUI ................................................................................................................................................. 8–19
I/O Characteristics for XSBI, XGMII & XAUI ................................................................................. 8–21
Software Implementation .............................................................................................................. 8–22
AC/DC Specifications ................................................................................................................... 8–22
10-Gigabit Ethernet MAC Core ....................................................................................................8–24
Conclusion ....................................................................................................................................... 8–25
Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices
Introduction ............................................................................................................................................ 9–1
System Topology .............................................................................................................................. 9–3
Interface Implementation in Stratix & Stratix GX Devices ......................................................... 9–5
AC Timing Specifications .............................................................................................................. 9–10
Electrical Specifications ................................................................................................................. 9–12
Software Implementation .............................................................................................................. 9–13
Conclusion ....................................................................................................................................... 9–13
Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices
Introduction .......................................................................................................................................... 10–1
General Architecture ........................................................................................................................... 10–1
Logic Elements ................................................................................................................................ 10–2
MultiTrack Interconnect ................................................................................................................ 10–3
DirectDrive Technology ................................................................................................................ 10–4
Architectural Element Names ...................................................................................................... 10–5
TriMatrix Memory ............................................................................................................................... 10–8
Same-Port Read-During-Write Mode ........................................................................................ 10–10
Mixed-Port Read-During-Write Mode ...................................................................................... 10–11
Memory Megafunctions .............................................................................................................. 10–12
FIFO Conditions ........................................................................................................................... 10–13
Design Migration Mode in Quartus II Software ...................................................................... 10–13
DSP Block ............................................................................................................................................ 10–16
DSP Block Megafunctions ........................................................................................................... 10–16
PLLs & Clock Networks ................................................................................................................... 10–18
Clock Networks ............................................................................................................................ 10–18
PLLs ................................................................................................................................................ 10–19
I/O Structure ...................................................................................................................................... 10–25
External RAM Interfacing ........................................................................................................... 10–25
I/O Standard Support ................................................................................................................. 10–26
High-Speed Differential I/O Standards .................................................................................... 10–26
altlvds Megafunction ................................................................................................................... 10–29
Configuration ..................................................................................................................................... 10–30