7. The Switch Interface ASIC sends bandwidth requests through the switch fabric to the
destination port. The Switch Interface ASIC also issues read requests to the Queuing
and Memory Interface ASIC to begin reading data cells out of memory.
8. The destination Switch Interface ASIC sends bandwidth grants through the switch
fabric to the originating Switch Interface ASIC.
9. Upon receipt of each bandwidth grant, the originating Switch Interface ASIC sends a
cell through the switch fabric to the destination Packet Forwarding Engine.
10. The destination Switch Interface ASIC receives cells from the switch fabric. It extracts
the route lookup key from each cell, places it in a notification, and forwards the
notification to the T Series Internet Processor.
11. The T Series Internet Processor performs the route lookup, and forwards the
notification to the Queuing and Memory Interface ASIC.
12. The Queuing and Memory Interface ASIC forwards the notification, including next-hop
information, to the Switch Interface ASIC.
13. The Switch Interface ASIC sends read requests to the Queuing and Memory Interface
ASIC to read the data cells out of memory, and passes the cells to the Layer 2/Layer
3 Packet Processing ASIC.
14. The Layer 2/Layer 3 Packet Processing ASIC reassembles the data cells into packets,
adds Layer 2 encapsulation, and sends the packets to the outgoing PIC interface.
15. The outgoing PIC sends the packets out into the network.
Related
Documentation
TX Matrix Router Overview on page 39•
Data Flow Through the TX Matrix Plus Router Packet Forwarding Engine
Data flows through the TX Matrix Plus router Packet Forwarding Engine in the following
sequence shown in Figure 33 on page 136.
135Copyright © 2012, Juniper Networks, Inc.
Chapter 4: Monitoring Key Router Components
To Next Page
Loading...
Need help?
General
