NXP Semiconductors LPC11U3x

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 311 of 523
NXP Semiconductors
UM10462
Chapter 14: LPC11U3x/2x/1x I2C-bus controller
Fig 49. Format and states in the Master Transmitter mode
DATA
A
R
WSLAS
DATAAW
SLA
to Master
receive
mode,
entry
= MR
MT
to corresponding
states in Slave mode
A OR AA OR A
A
other Master
continues
other Master
continues
A
other Master
continues
20H
08H
18H 28H
30H
10H
68H 78H B0H
38H 38H
arbitration lost
in Slave
address or
Data byte
Not
Acknowledge
received after a
Data byte
Not
Acknowledge
received after
the Slave
address
next transfer
started with a
Repeated Start
condition
arbitration lost
and
addressed as
Slave
successful
transmission
to a Slave
Receiver
from Master to Slave
from Slave to Master
any number of data bytes and their associated Acknowledge bits
n
this number (contained in I2STA) corresponds to a defined state of the
I
2
C bus
A P
P
S P