NXP Semiconductors LPC11U3x

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 491 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
24.5.3.3 Interrupt Control and State Register
The ICSR:
• provides:
– a set-pending bit for the Non-Maskable Interrupt (NMI) exception
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
• indicates:
– the exception number of the exception being processed
– whether there are preempted active exceptions
– the exception number of the highest priority pending exception
– whether any interrupts are pending.
See the register summary in Table 24–442
for the ICSR attributes. The bit assignments
are:
Table 443. CPUID register bit assignments
Bits Name Function
[31:24] Implementer Implementer code:
0x41 = ARM
[23:20] Variant Variant number, the r value in the rnpn product revision
identifier
[19:16] Constant Constant that defines the architecture of the processor:, reads
as
0xC = ARMv6-M architecture
[15:4] Partno Part number of the processor:
0xC20 = Cortex-M0
[3:0] Revision Revision number, the p value in the rnpn product revision
identifier