NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 517 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
12.5.6 USART FIFO Control Register (Write Only) . 248
12.5.7 USART Line Control Register. . . . . . . . . . . . 249
12.5.8 USART Modem Control Register . . . . . . . . . 250
12.5.8.1 Auto-flow control. . . . . . . . . . . . . . . . . . . . . . 251
12.5.8.1.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
12.5.8.1.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
12.5.9 USART Line Status Register (Read-Only) . . 253
12.5.10 USART Modem Status Register . . . . . . . . . 255
12.5.11 USART Scratch Pad Register . . . . . . . . . . . 255
12.5.12 USART Auto-baud Control Register . . . . . . 256
12.5.12.1 Auto-baud. . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.5.12.2 Auto-baud modes . . . . . . . . . . . . . . . . . . . . . 257
12.5.13 IrDA Control Register . . . . . . . . . . . . . . . . . 258
12.5.14 USART Fractional Divider Register . . . . . . . 260
12.5.14.1 Baud rate calculation . . . . . . . . . . . . . . . . . . 261
12.5.14.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR =
9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
12.5.14.1.2 Example 2: UART_PCLK = 12.0 MHz, BR =
115200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
12.5.15 USART Oversampling Register . . . . . . . . . . 263
12.5.16 USART Transmit Enable Register . . . . . . . 264
12.5.17 UART Half-duplex enable register . . . . . . . . 265
12.5.18 Smart Card Interface Control register . . . . . 265
12.5.19 USART RS485 Control register . . . . . . . . . 266
12.5.20 USART RS-485 Address Match register . . . 267
12.5.21 USART RS-485 Delay value register. . . . . . 267
12.5.22 USART Synchronous mode control register 268
12.6 Functional description . . . . . . . . . . . . . . . . . 270
12.6.1 RS-485/EIA-485 modes of operation. . . . . . 270
RS-485/EIA-485 Normal Multidrop Mode . . . 270
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
RS-485/EIA-485 Auto Direction Control. . . . . 271
RS485/EIA-485 driver delay time. . . . . . . . . . 271
RS485/EIA-485 output inversion . . . . . . . . . . 271
12.6.2 Smart card mode . . . . . . . . . . . . . . . . . . . . . 271
12.6.2.1 Smart card set-up procedure . . . . . . . . . . . . 272
12.7 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 273
Chapter 13: LPC11U3x/2x/1x SSP/SPI
13.1 How to read this chapter. . . . . . . . . . . . . . . . 275
13.2 Basic configuration . . . . . . . . . . . . . . . . . . . 275
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
13.4 General description. . . . . . . . . . . . . . . . . . . . 275
13.5 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 276
13.6 Register description . . . . . . . . . . . . . . . . . . . 276
13.6.1 SSP/SPI Control Register 0 . . . . . . . . . . . . . 277
13.6.2 SSP/SPI Control Register 1 . . . . . . . . . . . . . 278
13.6.3 SSP/SPI Data Register . . . . . . . . . . . . . . . . 279
13.6.4 SSP/SPI Status Register . . . . . . . . . . . . . . . 280
13.6.5 SSP/SPI Clock Prescale Register . . . . . . . . 280
13.6.6 SSP/SPI Interrupt Mask Set/Clear Register 280
13.6.7 SSP/SPI Raw Interrupt Status Register . . . . 281
13.6.8 SSP/SPI Masked Interrupt Status Register . 281
13.6.9 SSP/SPI Interrupt Clear Register . . . . . . . . 282
13.7 Functional description . . . . . . . . . . . . . . . . . 282
13.7.1 Texas Instruments synchronous serial frame
format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
13.7.2 SPI frame format . . . . . . . . . . . . . . . . . . . . . 283
13.7.2.1 Clock Polarity (CPOL) and Phase (CPHA)
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
13.7.2.2 SPI format with CPOL=0,CPHA=0. . . . . . . . 284
13.7.2.3 SPI format with CPOL=0,CPHA=1. . . . . . . . 285
13.7.2.4 SPI format with CPOL = 1,CPHA = 0. . . . . . 285
13.7.2.5 SPI format with CPOL = 1,CPHA = 1. . . . . . 287
13.7.3 Semiconductor Microwire frame format . . . . 287
13.7.3.1 Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 289
Chapter 14: LPC11U3x/2x/1x I2C-bus controller
14.1 How to read this chapter. . . . . . . . . . . . . . . . 290
14.2 Basic configuration . . . . . . . . . . . . . . . . . . . 290
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 290
14.5 General description. . . . . . . . . . . . . . . . . . . . 290
14.5.1 I
2
C Fast-mode Plus . . . . . . . . . . . . . . . . . . . 291
14.6 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 292
14.7 Register description . . . . . . . . . . . . . . . . . . . 292
14.7.1 I
2
C Control Set register (CONSET) . . . . . . . 293
14.7.2 I
2
C Status register (STAT). . . . . . . . . . . . . . . 295
14.7.3 I
2
C Data register (DAT). . . . . . . . . . . . . . . . . 295
14.7.4 I
2
C Slave Address register 0 (ADR0) . . . . . . 296
14.7.5 I
2
C SCL HIGH and LOW duty cycle registers
(SCLH and SCLL). . . . . . . . . . . . . . . . . . . . . 296
14.7.5.1 Selecting the appropriate I
2
C data rate and duty
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
14.7.6 I
2
C Control Clear register (CONCLR). . . . . . 297
14.7.7 I
2
C Monitor mode control register (MMCTRL) 297
14.7.7.1 Interrupt in Monitor mode. . . . . . . . . . . . . . . 298
14.7.7.2 Loss of arbitration in Monitor mode . . . . . . . 299
14.7.8 I
2
C Slave Address registers (ADR[1, 2, 3]) . 299
14.7.9 I
2
C Data buffer register (DATA_BUFFER) . . 299
14.7.10 I
2
C Mask registers (MASK[0, 1, 2, 3]) . . . . . 300
14.8 Functional description . . . . . . . . . . . . . . . . . 300
14.8.1 Input filters and output stages . . . . . . . . . . . 301
14.8.2 Address Registers, ADR0 to ADR3 . . . . . . . 302
14.8.3 Address mask registers, MASK0 to MASK3 302
14.8.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 302
14.8.5 Shift register, DAT . . . . . . . . . . . . . . . . . . . . 302
14.8.6 Arbitration and synchronization logic . . . . . . 302
14.8.7 Serial clock generator . . . . . . . . . . . . . . . . . 303
14.8.8 Timing and control . . . . . . . . . . . . . . . . . . . . 304
14.8.9 Control register, CONSET and CONCLR . . 304
14.8.10 Status decoder and status register. . . . . . . . 304
14.9 I
2
C operating modes. . . . . . . . . . . . . . . . . . . 304

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English