NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 519 of 523
NXP Semiconductors
UM10462
Chapter 25: Supplementary information
16.7.11 Count Control Register . . . . . . . . . . . . . . . . 362
16.7.12 PWM Control Register . . . . . . . . . . . . . . . . . 364
16.7.13 Rules for single edge controlled PWM outputs. . .
365
16.8 Example timer operation . . . . . . . . . . . . . . . 366
16.9 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 367
Chapter 17: LPC11U3x/2x/1x Windowed Watchdog Timer (WWDT)
17.1 How to read this chapter. . . . . . . . . . . . . . . . 369
17.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 369
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
17.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 370
17.5 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 370
17.5.1 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . 370
17.6 Clocking and power control . . . . . . . . . . . . . 371
17.7 Using the WWDT lock features. . . . . . . . . . . 372
17.7.1 Accidental overwrite of the WWDT clock . . . 372
17.7.2 Changing the WWDT clock source. . . . . . . . 372
17.7.3 Changing the WWDT reload value . . . . . . . 372
17.8 Register description . . . . . . . . . . . . . . . . . . . 373
17.8.1 Watchdog mode register . . . . . . . . . . . . . . . 373
17.8.2 Watchdog Timer Constant register. . . . . . . . 375
17.8.3 Watchdog Feed register. . . . . . . . . . . . . . . . 375
17.8.4 Watchdog Timer Value register . . . . . . . . . . 376
17.8.5 Watchdog Clock Select register. . . . . . . . . . 376
17.8.6 Watchdog Timer Warning Interrupt register . 376
17.8.7 Watchdog Timer Window register . . . . . . . . 377
17.9 Watchdog timing examples . . . . . . . . . . . . . 377
Chapter 18: LPC11U3x/2x/1x System tick timer
18.1 How to read this chapter. . . . . . . . . . . . . . . . 379
18.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 379
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
18.4 General description. . . . . . . . . . . . . . . . . . . . 379
18.5 Register description . . . . . . . . . . . . . . . . . . . 380
18.5.1 System Timer Control and status register . . 380
18.5.2 System Timer Reload value register . . . . . . 381
18.5.3 System Timer Current value register . . . . . 381
18.5.4 System Timer Calibration value register
(SYST_CALIB - 0xE000 E01C) . . . . . . . . . . 382
18.6 Functional description . . . . . . . . . . . . . . . . . 382
18.7 Example timer calculations . . . . . . . . . . . . . 382
Example (system clock = 50 MHz). . . . . . . . . 382
Chapter 19: LPC11U3x/2x/1x ADC
19.1 How to read this chapter. . . . . . . . . . . . . . . . 383
19.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 383
19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
19.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 383
19.5 Register description . . . . . . . . . . . . . . . . . . . 384
19.5.1 A/D Control Register (CR - 0x4001 C000) . . 385
19.5.2 A/D Global Data Register
(GDR - 0x4001 C004). . . . . . . . . . . . . . . . . . 386
19.5.3 A/D Interrupt Enable Register (INTEN -
0x4001 C00C) . . . . . . . . . . . . . . . . . . . . . . . 387
19.5.4 A/D Data Registers (DR0 to DR7 - 0x4001 C010
to 0x4001 C02C) . . . . . . . . . . . . . . . . . . . . . 387
19.5.5 A/D Status Register (STAT - 0x4001 C030). 387
19.6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
19.6.1 Hardware-triggered conversion . . . . . . . . . . 388
19.6.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
19.6.3 Accuracy vs. digital receiver . . . . . . . . . . . . 388
Chapter 20: LPC11U3x/2x/1x Flash programming firmware
20.1 How to read this chapter. . . . . . . . . . . . . . . . 389
20.2 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
20.4 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 390
20.5 Memory map after any reset . . . . . . . . . . . . . 391
20.6 Flash content protection mechanism . . . . . 391
20.7 Criterion for Valid User Code . . . . . . . . . . . . 392
20.8 ISP/IAP communication protocol. . . . . . . . . 393
20.8.1 ISP command format . . . . . . . . . . . . . . . . . . 393
20.8.2 ISP response format. . . . . . . . . . . . . . . . . . . 393
20.8.3 ISP data format. . . . . . . . . . . . . . . . . . . . . . . 393
20.8.4 ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 393
20.8.5 ISP command abort . . . . . . . . . . . . . . . . . . . 393
20.8.6 Interrupts during ISP. . . . . . . . . . . . . . . . . . . 393
20.8.7 Interrupts during IAP . . . . . . . . . . . . . . . . . . 394
20.8.8 RAM used by ISP command handler. . . . . . 394
20.8.9 RAM used by IAP command handler. . . . . . 394
20.9 USB communication protocol . . . . . . . . . . . 394
20.9.1 Usage note. . . . . . . . . . . . . . . . . . . . . . . . . . 395
20.10 Boot process flowchart . . . . . . . . . . . . . . . . 396
20.11 Sector numbers. . . . . . . . . . . . . . . . . . . . . . . 397
20.11.1 LPC11U1x/2x . . . . . . . . . . . . . . . . . . . . . . . . 397
20.11.2 LPC11U3x . . . . . . . . . . . . . . . . . . . . . . . . . . 397
20.12 Code Read Protection (CRP) . . . . . . . . . . . . 398
20.12.1 ISP entry protection . . . . . . . . . . . . . . . . . . . 400
20.13 ISP commands . . . . . . . . . . . . . . . . . . . . . . . 401
20.13.1 Unlock <Unlock code>. . . . . . . . . . . . . . . . . 401
20.13.2 Set Baud Rate <Baud Rate> <stop bit>. . . . 402

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English