Oki IP-6620 - Page 557

OKI Data Infotech Corporation CONFIDENTIAL
Chapter 8 Operation Mechanism
8-36
Board name
DC power
Connected to
IPB5 board
38 V
P5V generation
5 V
Logic IC, 3.3 V generation, 1.9 V generation
3.3 V
Logic IC, FPGA I/O, 1.2 V generation
1.9 V
SH3 core
1.2 V
FPGA core
ACT3 board
38 V
P12V generation, P5V generation, P3.3V generation, P24VSF
generation (suction fan power supply), P24VRF generation (rear fan
power supply), X motor, Y motor, HCB1M board
24 V
Capping motor, cap up/down motor, interlock relay, suction
pump/wipe motor, air release solenoid, electrical unit cooling fan,
PSU cooling fan, exhaust fan, take-up motors, ink supply motor
12 V
Y motor driving circuit
5 V
Logic IC, sensors, P3.3V generation
3.3 V
Logic IC, FPGA I/O, P1.2V generation
1.2 V
FPGA core
HCB1M board
38 V
P5V generation, VDD2 generation, P12V generation, head heater
VDD2
Head
12 V
Ionizer, automatic print adjustment
24 V
Head cooling fan
5 V
Logic IC, sensors, P3.3V generation, PREF generation, automatic
print adjustment
3.3 V
Logic IC, P1.2V generation, FPGA I/O
1.2 V
FPGA core
MCP4M board
MCP5 board
5 V
Logic IC, LCD backlight
3.3 V
Logic IC, CPLD, LCD module