Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 165
UG366 (v2.5) January 17, 2011
TX Pattern Generator
To calculate accurately the receiver’s BER (bit error rate), an external jitter tolerance tester
should be used. For the test, the GTX transceiver should loop received error status back
through the transmitter by setting RXPRBSERR_LOOPBACK to 1 (Figure 3-27). The same
setting should be applied to RXENPRBSTST and TXENPRBSTST.
X-Ref Target - Figure 3-26
Figure 3-26: Link Test Mode with a PRBS-7 Pattern
UG366_c3_16_051509
TX Pattern
Generator
RX Pattern
Checker
001
001
RX Pattern
Checker
TX Pattern
Generator
001
001
RXPRBSERR_LOOPBACK = 0
TXENPRBSTST
TXPRBSFORCEERR
RXENPRBSTST
RXPRBSERR
RX_PRBS_ERR_CNT
RXENPRBSTST
RXPRBSERR
RX_PRBS_ERR_CNT
RXPRBSERR_LOOPBACK = 0
TXENPRBSTST
TXPRBSFORCEER
X-Ref Target - Figure 3-27
Figure 3-27: Jitter Tolerance Test Mode with a PRBS-7 Pattern
UG366_c3_17_061809
RX Pattern
Checker
TX Pattern
Generator
RXENPRBSTST
001
RXPRBSERR
TXENPRBSTST
TXPRBSFORCEERR
001
Jitter Tester
TX
PRBS-7 Pattern
with Jitter
RX
Pattern Checker
RXPRBSERR_LOOPBACK = 1
RX_PRBS_ERR_CNT
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English