Xilinx Virtex-6 FPGA User Manual

272 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 4: Receiver
Table 4-61 defines the FPGA RX attributes.
RXUSRCLK In Clock This port provides a clock for the internal RX PCS datapath. In
some use cases, this clock is internally generated. See Table 4-58.
RXUSRCLK2 In Clock This port synchronizes the FPGA logic with the RX interface.
This clock must be positive-edge aligned to RXUSRCLK when
RXUSRCLK is provided by the user.
Table 4-60: FPGA RX Ports (Cont’d)
Port Dir Clock Domain Description
Table 4-61: FPGA RX Attributes
Attribute Type Description
GEN_RXUSRCLK Boolean Controls internal generation of RXUSRCLK available in certain modes of
operation. See RXUSRCLK and RXUSRCLK2 Generation, page 270.
TRUE: RXUSRCLK internally generated. RXUSRCLK must be tied Low.
FALSE: RXUSRCLK must be provided by user.
RX_DATA_WIDTH Integer Sets the bit width of the RXDATA port. When 8B/10B decoding is enabled,
RX_DATA _WIDTH must be set to 10, 20, or 40. Valid settings are 8, 10, 16, 20,
32, and 40.
See Interface Width Configuration, page 269 for more details.
www.BDTIC.com/XILINX

Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English