Altera Stratix - Page 297

Altera Corporation 7–11
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Figure 7–5. Serial Loading 18-Bit 8-Tap FIR Filter Using Two DSP Blocks
Notes (1), (2), (3)
Notes to Figure 7–5:
(1) Unused ports grayed out.
(2) The indexing x(n-1), ..., x(n-7) refers to the case of parallel loading and should be
ignored here. This indexing is retained in this figure for consistency with other
figures in this chapter.
(3) To increase the DSP block performance, include the pipeline and output registers.
See Figure 7–3 on page 7–8 for the details.
DQ
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
DSP block 1
Filter output
y(n)
h(0)
h
(
1
)
h
(
2
)
h
(
3
)
x(n)
Filter coefficients
Data input
x
(n-2)
x
x
x
(n-3)
xx
x
(n-1)
x
x
h
(
4
)
h
(5
)
h
(
6
)
h(7)
x
(n-4)
xx
x
(n-5)
xx
x
(n-6)
x
x
x
(n-7)
xx
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
DQ
DSP block 2