Altera Stratix - Page 386

9–8 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Introduction
Figure 9–6. Framer Receiver Interface in Stratix & Stratix GX Devices
Note to Figure 9–6:
(1) The figure shows Stratix GX DPA disabled.
f For more information on the byte-alignment feature in Stratix and
Stratix GX devices, see the High-Speed Differential I/O Interfaces in Stratix
Devices chapter in the Stratix Device Handbook or the Stratix GX Device
Handbook.
RXDATA[0]
Fast PLL
W = 1
J = 8
8
8
Stratix & Stratix GX SERDES
× W
CH0
CH15
OC-192
SERDES
RXDATA[15]
RXCLK
Stratix & Stratix GX SFI-4 Receiver
÷J
622 MHz
622 MHz
Parallel
Register
Serial-to-Parallel
Register
622 Mbps
Stratix & Stratix GX
Logic Array