Altera Stratix - Page 460

11–34 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
PPA Configuration Timing
Figure 11–18 shows the Stratix and Stratix GX device timing waveforms
for PPA configuration.
Figure 11–18. PPA Timing Waveforms for Stratix & Stratix GX Devices
Notes to Figure 11–18:
(1) Upon power-up, nSTATUS is held low for the time of the POR delay.
(2) Upon power-up, before and during configuration, CONF_DONE is low.
(3) After configuration, the state of CS, nCS, nWS, and RDYnBSY depends on the design programmed into the Stratix or
Stratix GX device.
(4) Device I/O pins are in user mode.
Byte 0
Byte 1
t
DH
t
WSP
t
CF2WS
nCONFIG
nSTATUS
( 1)
CONF_DONE ( 2)
DATA[7..0]
CS ( 3)
nCS ( 3)
nWS ( 3)
RDYnBSY ( 3)
Byte n Ð 1 Byte n
t
BUSY
t
WS2B
t
RDY2WS
t
CFG
t
STATUS
User I/Os
INIT_DONE
High-Z
t
CF2ST0
t
CF2CD
( 4)
( 4)
( 4)
( 4)
( 4)
t
CF2ST1
t
DSU
t
CSSU
t
CSH
t
CD2UM
t
CSSU