NXP Semiconductors LPC11U3x User Manual

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 21 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
In addition to the system control block registers described in Table 5, the flash access
timing register, which can be re-configured as part the system setup, is described in
Table 6
. This register is not part of the system configuration block.
All address offsets not shown in Table 5
and Table 6 are reserved and should not be
written.
Table 5. Register overview: system control block (base address 0x4004 8000)
Name Access Offset Description Reset value Reset value
after boot
Reference
SYSMEMREMAP R/W 0x000 System memory remap 0x02 0x02 Table 7
PRESETCTRL R/W 0x004 Peripheral reset control 0 0 Table 8
SYSPLLCTRL R/W 0x008 System PLL control 0 0 Table 9
SYSPLLSTAT R 0x00C System PLL status 0 0 Table 10
USBPLLCTRL R/W 0x010 USB PLL control 0 0 Table 11
USBPLLSTAT R 0x014 USB PLL status 0 0 Table 12
SYSOSCCTRL R/W 0x020 System oscillator control 0 0 Table 13
WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0 0 Table 14
IRCCTRL R/W 0x028 IRC control 0x080 - Table 15
- - 0x02C Reserved - - -
SYSRSTSTAT R/W 0x030 System reset status register 0x3 0x3 Table 16
SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0x1 0x1 Table 17
SYSPLLCLKUEN R/W 0x044 System PLL clock source update
enable
0x1 0x1 Table 18
USBPLLCLKSEL R/W 0x048 USB PLL clock source select 0 0 Table 19
USBPLLCLKUEN R/W 0x04C USB PLL clock source update enable 0 0 Table 20
MAINCLKSEL R/W 0x070 Main clock source select 0 0 Table 21
MAINCLKUEN R/W 0x074 Main clock source update enable 0x1 0x1 Table 22
SYSAHBCLKDIV R/W 0x078 System clock divider 0x1 0x1 Table 23
SYSAHBCLKCTRL R/W 0x080 System clock control 0x3F 0x0800485F Table 24
SSP0CLKDIV R/W 0x094 SSP0 clock divider 0 0x1 Table 25
UARTCLKDIV R/W 0x098 UART clock divider 0 0 Table 26
SSP1CLKDIV R/W 0x09C SSP1 clock divider 0 0 Table 27
- - 0x0A0 -
0x0BC
Reserved - - -
USBCLKSEL R/W 0x0C0 USB clock source select 0 0 Table 28
USBCLKUEN R/W 0x0C4 USB clock source update enable 0 0 Table 29
USBCLKDIV R/W 0x0C8 USB clock source divider 0 0x1 Table 30
- - 0x0CC Reserved - -
CLKOUTSEL R/W 0x0E0 CLKOUT clock source select 0 0 Table 31
CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0 0 Table 32
CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0 0 Table 33
PIOPORCAP0 R 0x100 POR captured PIO status 0 user dependent user
dependent
Table 34
PIOPORCAP1 R 0x104 POR captured PIO status 1 user dependent user
dependent
Table 35

NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English