NXP Semiconductors LPC11U3x

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 363 of 523
NXP Semiconductors
UM10462
Chapter 16: LPC11U3x/2x/1x 32-bit counter/timers CT32B0/1
Remark: The bit positions for the CAP1 channel count input select (CIS) and edge select
bits (SELCC) are different for counter/timers CT16B0 (Table 333
) and CT16B1
(Table 334
).
Table 333: Count Control Register (CTCR, address 0x4001 4070 (CT32B0)) bit description
Bit Symbol Value Description Reset
value
1:0 CTM Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or
clear PC and increment Timer Counter (TC).
Remark: If Counter mode is selected in the CTCR, bits 2:0 in
the Capture Control Register (CCR) must be programmed as
000.
00
0x0 Timer Mode: every rising PCLK edge
0x1 Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
0x2 Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
0x3 Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
3:2 CIS Count Input Select. In counter mode (when bits 1:0 in this
register are not 00), these bits select which CAP pin is
sampled for clocking.
Remark: If Counter mode is selected in the CTCR, the 3 bits
for that input in the Capture Control Register (CCR) must be
programmed as 000. Values 0x1 and 0x3 are reserved.
00
0x0 CT32B0_CAP0
0x1 Reserved.
0x2 CT32B0_CAP1
4 ENCC Setting this bit to 1 enables clearing of the timer and the
prescaler when the capture-edge event specified in bits 7:5
occurs.
0
7:5 SElCC When bit 4 is a 1, these bits select which capture input edge
will cause the timer and prescaler to be cleared. These bits
have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6
to 0x7 are reserved.
0x0 Rising Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)
0x1 Falling Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)
0x2 Reserved,
0x3 Reserved.
0x4 Rising Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)
0x5 Falling Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)
31:8 - - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
-