UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 420 of 523
NXP Semiconductors
UM10462
Chapter 20: LPC11U3x/2x/1x Flash programming firmware
20.16.4.2 Flash signature generation
The flash module contains a built-in signature generator. This generator can produce a
128-bit signature from a range of flash memory. A typical usage is to verify the flashed
contents against a calculated signature (e.g. during programming).
The address range for generating a signature must be aligned on flash-word boundaries,
i.e. 128-bit boundaries. Once started, signature generation completes independently.
While signature generation is in progress, the flash memory cannot be accessed for other
purposes, and an attempted read will cause a wait state to be asserted until signature
generation is complete. Code outside of the flash (e.g. internal RAM) can be executed
during signature generation. This can include interrupt services, if the interrupt vector
table is re-mapped to memory other than the flash memory. The code that initiates
signature generation should also be placed outside of the flash memory.
20.16.4.3 Signature generation address and control registers
These registers control automatic signature generation. A signature can be generated for
any part of the flash memory contents. The address range to be used for generation is
defined by writing the start address to the signature start address register (FMSSTART)
and the stop address to the signature stop address register (FMSSTOP). The start and
stop addresses must be aligned to 128-bit boundaries and can be derived by dividing the
byte address by 16.
Signature generation is started by setting the SIG_START bit in the FMSSTOP register.
Setting the SIG_START bit is typically combined with the signature stop address in a
single write.
Table 402
and Table 403 show the bit assignments in the FMSSTART and FMSSTOP
registers respectively.
Table 401. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description
Bit Symbol Value Description Reset
value
1:0 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the
number of system clocks used for flash access.
0x2
0x0 1 system clock flash access time (for system clock
frequencies of up to 20 MHz).
0x1 2 system clocks flash access time (for system clock
frequencies of up to 40 MHz).
0x2 3 system clocks flash access time (for system clock
frequencies of up to 50 MHz).
0x3 Reserved
31:2 - - Reserved. User software must not change the value of
these bits. Bits 31:2 must be written back exactly as read.
-
Table 402. Flash module signature start register (FMSSTART - 0x4003 C020) bit description
Bit Symbol Description Reset
value
16:0 START Signature generation start address (corresponds to AHB byte
address bits[20:4]).
0
31:17 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
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