NXP Semiconductors LPC11U3x

UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 432 of 523
24.1 Introduction
The following material is using the ARM Cortex-M0 User Guide. Minor changes have
been made regarding the specific implementation of the Cortex-M0 for the
LPC11U3x/2x/1x.
24.2 About the Cortex-M0 processor and core peripherals
The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers,
including:
• a simple architecture that is easy to learn and program
• ultra-low power, energy efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family.
The Cortex-M0 processor is built on a highly area and power optimized 32-bit processor
core, with a 3-stage pipeline von Neumann architecture. The processor delivers
exceptional energy efficiency through a small but powerful instruction set and extensively
optimized design, providing high-end processing hardware including a single-cycle
multiplier.
The Cortex-M0 processor implements the ARMv6-M architecture, which is based on the
16-bit Thumb instruction set and includes Thumb-2 technology. This provides the
exceptional performance expected of a modern 32-bit architecture, with a higher code
density than other 8-bit and 16-bit microcontrollers.
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
Rev. 5.5 — 21 December 2016 User manual
Fig 74. Cortex-M0 implementation
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