UM10462 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
User manual Rev. 5.5 — 21 December 2016 433 of 523
NXP Semiconductors
UM10462
Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
The Cortex-M0 processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
• includes a non-maskable interrupt (NMI).
• provides zero jitter interrupt option.
• provides four interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart
load-multiple and store-multiple operations. Interrupt handlers do not require any
assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining
optimization also significantly reduces the overhead when switching from one ISR to
another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
Deep-sleep function that enables the entire device to be rapidly powered down.
24.2.1 System-level interface
The Cortex-M0 processor provides a single system-level interface using AMBA
technology to provide high speed, low latency memory accesses.
24.2.2 Integrated configurable debug
The Cortex-M0 processor implements a complete hardware debug solution, with
extensive hardware breakpoint and watchpoint options. This provides high system
visibility of the processor, memory and peripherals through a 2-pin Serial Wire Debug
(SWD) port that is ideal for microcontrollers and other small package devices.
24.2.3 Cortex-M0 processor features summary
• high code density with 32-bit performance
• tools and binary upwards compatible with Cortex-M processor family
• integrated ultra low-power sleep modes
• efficient code execution permits slower processor clock or increases sleep mode time
• single-cycle 32-bit hardware multiplier
• zero jitter interrupt handling
• extensive debug capabilities.
24.2.4 Cortex-M0 core peripherals
These are:
NVIC — The NVIC is an embedded interrupt controller that supports low latency interrupt
processing.
System Control Block — The System Control Block (SCB) is the programmers model
interface to the processor. It provides system implementation information and system
control, including configuration, control, and reporting of system exceptions.
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