NXP Semiconductors LPC11U3x User Manual

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User manual Rev. 5.5 — 21 December 2016 441 of 523
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Chapter 24: LPC11U3x/2x/1x Appendix ARM Cortex-M0
The processor reserves regions of the Private peripheral bus (PPB) address range for
core peripheral registers, see Section 24–24.2
.
24.3.2.1 Memory regions, types and attributes
The memory map is split into regions. Each region has a defined memory type, and some
regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
The memory types are:
Normal — The processor can re-order transactions for efficiency, or perform speculative
reads.
Device — The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
For the LPC11U3x/2x/1x specific implementation of the memory map, see Figure 4.
Fig 77. Cortex-M0 memory map
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NXP Semiconductors LPC11U3x Specifications

General

Brand	NXP Semiconductors
Model	LPC11U3x
Category	Microcontrollers
Language	English